Layerscape Architecture

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Layerscape Architecture is an evolution of the QorIQ processor family from NXP semiconductors (formerly Freescale Semiconductor). Layerscape product families are the first of the QorIQ processors to support the Arm instruction set. The modular Layerscape architecture consists of three independent, scalable layers, allowing Freescale to design QorIQ devices with expanded, reduced or removed layers as needed, providing the optimal solution for a given application. LS1 and LS2 families use Cortex A7, A9, A53 and A72 cores.^[1]

LS1 means LS1XXX series (e.g., LS1021A, etc.); LS2 means LS2XXX series. LS2 means a higher performance level than LS1, and it does not indicate a second generation. The middle two digits of the product name are core count; the last digit distinguishes models, with, in most but not all cases, a higher digit meaning greater performance. “A” at the end indicates the Arm processor. LX designates the 16 nm FinFET generation.

The LS1 family is built on the Layerscape architecture, the industry’s first software-aware, core-agnostic networking architecture. Both LS1 and LS2 families of processors offer the advanced, high-performance datapath and network peripheral interfaces required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications.

Initial announcement

Freescale Semiconductor Inc. (acquired by NXP Semiconductors in late 2015) announced a core-agnostic network processor system architecture said to offer the flexibility and scalability required by network infrastructure OEMs to handle an exploding number of connected devices, massive datasets, tight security, real-time service and increasingly unpredictable network traffic patterns. It modularizes packet acceleration and forwarding operations from high-level routing decisions, streamlines interaction between the layers and leverages a synchronous run-to-completion model. Layerscape devices also support a consistent programming framework across the architecture using standard C/C++ languages. NXP also announced the first two QorIQ product families based on the Layerscape architecture, the LS1 and LS2. These products included dual Arm Cortex processor cores, virtualization support, advanced security, an array of advanced interconnects, a common ISA and software- and pin-compatibility for simple and smooth application migration between the two families.

First products

The first two product families based on the Layerscape architecture are the LS1 and LS2. Highlights of the families include dual Arm Cortex processor cores, virtualization support, advanced security, an array of advanced interconnects, a common ISA, and software- and pin-compatibility for simple and smooth application migration between the two families.

The LS1 family features two Arm Cortex-A7 cores running at up to 1.2 GHz. The LS2 family features two Arm Cortex-A15 cores running at up to 1.5 GHz and under 5W total power. Targeted applications for the LS1 and LS2 families include residential gateways, enterprise access points, smart energy systems, industrial communications, line cards and robotics.

The pin- and software-compatible LS1 family initially included three products:

• The highly integrated LS1020A processor, ideal for fanless enterprise and consumer networking applications, such as enterprise access points, multi-protocol IoT gateways and security appliances
• The LS1021A processor, which adds integrated display controller and industrial interfaces for use in factory/building automation, M2M, printing and defense/aerospace applications. The LS1021A processor features two high-efficiency Arm Cortex-A7 cores, enhanced with error checking and correction (ECC) technology, delivering outstanding performance at a typical power of fewer than 3 W.
• The cost-optimized LS1022A processor, which offers high-reliability performance for the most power-sensitive industrial applications with extremely aggressive power envelopes.

In 2014, Freescale Semiconductors introduced LS2 series, LS2085A and LS2045A (both retired) featuring: eight and four 64-bit Arm Cortex-A57 cores respectively, running up to 2GHz; DDR4 memory controllers; eight 10Gb interfaces; and eight 1Gb interfaces with L2 switch capabilities. The products’ datapath engine is capable of 40 Gb/s complex packet processing with acceleration technology. The LS2 family is specifically designed for SDN/OpenFlow switching, NFV solutions, wireless access, enterprise routing, and data center processing applications. Tightly coupled to this domain is a set of debug, I/O and acceleration technologies, including a packet processing engine. This data plane engine is C-programmable. Additionally, the LS2 packet processor is enabled with a vast toolkit of turnkey, C-based libraries of common networking protocols and functions which provide a link between flexibility and performance. Also included in the architecture, and designed to work closely with the datapath engine, is an integrated L2 switch, enabling interconnect and peripherals to provide a complete system-on-chip.

Acquisition of Comcerto Business

In April of 2014, Freescale acquired a portion of Mindspeed Technologies, which produced Arm-based multicore embedded processors and associated software targeting systems such as home gateways and network-attached storage. Mindspeed had just been acquired M/A-Com Technology Solutions, and the latter sought to sell off portions of Mindspeed that were not essential to its strategy. Chief among the Mindspeed products is the Comcerto 2000 SoC, which combines two 1.2 GHz Arm Cortex-A9 CPUs with packet engines and communications accelerators. This chip became LS1024A processor of Freescale, and the company marketed it widely.

First Quad-core Networking SoC with Arm v8 A53

Later in the year, Freescale also announced LS1043A communication processor. The SoC, which allows fanless designs, delivers 1.5 GHz of performance and requires power as low as just 6 W to operate. the LS1043A device integrates four 64-bit Arm Cortex-A53 cores, delivering 10+ Gbps and an estimated 16,000+ Coremarks of CPU performance. The device features advanced virtualization hardware, supports flexible, secure cloud application updates with Freescale’s trust architecture, and offloads latency sensitive applications for optimized local performance with proven classification and traffic management hardware.

For maximum configuration flexibility, the LS1043A includes a wide range of high-speed I/O for wired and wireless systems including 10 GbE plus 5x 1GbE, 3x PCI Express, 3x USB 3.0 with PHYs and SATA 3.0. Freescale’s multi-protocol QUICC Engine module is also incorporated for integrated support of legacy wide area and industrial interfaces.

Recent Products

In the summer of 2015, Freescale introduced the LS1088A octal and LS1048A quad multicore processors based on the performance-optimized and power-conscious 64-bit capable Arm Cortex-A53 cores. The LS1088A and LS1048A processors feature Cortex-A53 cores running up to 1.5 GHz. The devices deliver exceptional integration, incorporating DDR4 memory controllers and up to two 10 Gb/s and eight 1 Gb/s Ethernet interfaces with L2 switch capabilities. These ultra-low-power processors are specifically designed for intelligent edge access equipment, NFV and virtual CPE solutions, industrial control systems and intelligent NIC applications.

In February of 2016, NXP introduced the LS1012A. NXP combined a low-power, 2 Gbps packet crypto accelerator with a highly power-efficient 64-bit Arm Cortex-A53 core, and integrated them with a full suite of high speed peripherals. The product incorporates dual 2.5 Gigabit Ethernet, PCIe, SATA3 and USB 3.0 with integrated PHY. The processor can be routed on 4-layer PCBs.

First Quad-core Networking SoC with Arm v8 A-72

In March of 2016, NXP also introduced the LS1046A processor, which is the industry’s lowest power quad-core Arm Cortex-A72 based device (at the time of the launch). LS1046A is available in a 23 x 23 mm package and is compatible with NXP’s LS1023A, LS1043A and LS1088A SoCs. LS1046A offers performance above 32,000 Coremarks, and integrates 10 GB Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces.

Multi-standard Platform for 5G Evolution

In February 2017 NXP announced a new family of fully programmable, multi-standard SoCs for multi-access technologies including 5G evolution. The Layerscape LA family targets scalable solutions in wired and wireless enterprise and carrier networks, and home gateway markets. The family enables rapid deployment of next generation platforms into these markets with fully programmable technology.

The architecture offers an innovative, programmable MAC and PHY layer modem technology, which provides a scalable, unified hardware + software solution that can accommodate multiple modem implementations across Wi-Fi, 5G and other applications. It optimizes for flexibility, time-to-market and diversification of deployment options.

The first product in the family, the LA1575, solves a multi-standard problem with simultaneous implementation of 802.11ax, 802.11ad, and millimeter wave (mmWave) standards on a single SoC device. Initial targets include enterprise and high-end home gateway markets. The LA1575 integrates the fully programmable PHY and MAC with acceleration technologies for 5G, Wi-Fi and wireline protocols that allow updates, changes, and new features to be added via simple software upgrades.

Integrated Time-Sensitive Networking Platform for the Industrial IoT

In March of 2017, NXP announced the LS1028A, integrating Time-Sensitive Networking (TSN) capabilities based on the IEEE 802.1 standards. The LS1028A builds on NXP’s Layerscape family of SoCs while adding significant capabilities, including upgraded 64-bit Arm Cortex v8 processor cores, an integrated 3D GPU and LCD controller, a four-port TSN switch and two separate TSN Ethernet controllers.  The combination of time sensitive networking with a GPU enable the SoC to address industrial human machine interface and control applications.  The device is built on NXP’s Trust Architecture, which provides a root of trust, securing applications and services.  It is designed to support both TSN bridging applications as well as TSN endpoint applications and will be offered with a 15-year manufacturing promise. LS1028A is preproduction silicon (As of April 2018).

Sixteen-core Networking SoC with Arm v8 A72

In October of 2017, NXP announced the highest performance member of the Layerscape family, the LX2160A SoC. The LX2160A is specifically designed to enable challenging high-performance network applications, network edge compute, and data center offloads. Trusted and secure execution of virtualized cloud workloads at the edge is driving new distributed computing paradigms.

The LX2160A features sixteen high-performance Arm Cortex-A72 cores running at over 2 GHz in a sub 30-watt power envelope, supporting both the 100 Gbit/s Ethernet and PCIe Gen4 interconnect standards. In addition, it provides L2 switching at wire rate and includes acceleration for data compression and 50 Gbit/s IPSec cryptography.

NXP supports and drives the rich Arm ecosystem for virtualization, building on the foundations of open source projects for cloud and network function virtualization including Open Daylight, OpenStack, and OP-NFV. NXP Arm processors incorporate hardware for virtualization technologies such as KVM and Linux containers and hardware acceleration of network virtualization. NXP also supports industry-standard APIs for virtualization, including DPDK, OVS, and Virtio, and standard enterprise Linux distributions, such as Debian and Ubuntu.

Layerscape Product Family List

						Security
Device	Cores	Frequency	PCIe	SerDES	SATA	Integrated SEC Engine	DCE/PME	QE
LS1012A	1 x Arm Cortex A53	1.0 GHz	1 x Gen2.0	3 lanes 6 GHz	Yes	Yes	-	-
LS1020A	2 x Arm Cortex A7	1.2 GHz	2 x Gen2.0	4 lanes 6 GHz	Yes	Yes	-	Yes
LS1021A	2 x Arm Cortex A7	1.2 GHz	2 x Gen2.0	4 lanes 6 GHz	Yes	Yes	-	Yes
LS1022A	2 x Arm Cortex A7	0.6 GHz	1 x Gen2.0	1 lane 5 GHz	No	Yes	-	-
LS1024A	2 x Arm Cortex A9	1.2 GHz	2 x Gen2.0	3 lanes 5 GHz	Yes	Yes	Yes	-
LS1028A	2 x Arm Cortex A72	1.3 GHz	2 x Gen2.0	4 lanes 10 GHz	Yes	Yes	-	-
LS1043A	4 x Arm Cortex A53	1.6 GHz	3 x Gen2.0	4 lanes 10 GHz	Yes	Yes	-	Yes
LA1575	2 x Arm Cortex A53	1.4 GHz	1 x Gen3.0	4 lanes 10 GHz	Yes	Yes	-	-
LS1046A	4 x Arm Cortex A72	1.8 GHz	3 x Gen3.0	8 lanes 10 GHz	Yes	Yes	-	-
LS1088A	8 x Arm Cortex A53	1.6 GHz	3 x Gen3.0	4 lanes 10 GHz	Yes	Yes	-	Yes
LX2160A	16 x Arm Cortex A72	2.2 GHz	6x Gen 4.0	24 lanes 25 GHz	Yes	Yes	100 Gbps

Layerscape

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