Debendra Das Sharma, PhD
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| Debendra Das Sharma, PhD | |
|---|---|
| Born | |
| 💼 Occupation | |
| 👔 Employer | Intel |
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Debendra Das Sharma is an Intel Senior Fellow, based in Santa Clara, California, leading the I/O Technology and Standards group. He is responsible for delivering Intel-wide interconnect technologies in Peripheral Component Interconnect Express (PCI Express®), Compute Express Link (CXLTM), Universal Chiplet Interconnect Express (UCIe™), Intel’s Cache Coherency Interconnect (Ultra Path Interconnect), and Rack Scale Architecture. He leads the path-finding, architectural specification, design and external ecosystem enabling all of these I/O technologies.[1]
Career[edit]
Das Sharma joined Hewlett-Packard Company in 1994 after completing his Ph.D., Das Sharma was responsible for leading the development of the server chipsets at HP. He led HP’s transition to PCI based I/O from its proprietary I/O bus as well as the transition to link-based coherent interfaces from bus-based systems in the Superdome servers.[2]
Das Sharma joined Intel Corporation in 2001, as part of Intel’s acquisition of his server chipset team. He led the development of PCI Express specification, product design, and the integration of PCIe in server CPUs. He also led the development of Intel’s Quick Path Interconnect based systems, marking a transition from the Front-Side Bus based interconnect to point-to-point full duplex differential coherency interconnect. He was promoted to the position of Principal Engineer in 2004, Senior Principal Engineer in 2010, Intel Fellow in 2018, and Intel Senior Fellow in 2022.[3]
Das Sharma has been leading the development of PCI Express (PCIe) since its inception through six generations of the technology evolution. He has played a key role in evolving PCI Express as the ubiquitous I/O interconnect in the industry, spanning the entire compute continuum. He is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) – a consortia with more than 900 member companies, responsible for the development of PCI Express technology.[4] He is a founder of the Compute Express Link consortium with more than 200 companies where is chairs the CXL Board Technical Task Force to drive CXL technology.[5] He chairs the Universal Chiplet Interconnect Express (UCIe) consortium which he established in March 2022.[6] Das Sharma also leads the development and evolution of PHY Interface for PCI Express (PIPE), which is the de-facto industry standard for System on a Chip (SoC) development, for designing PCIe, Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Display Port (DP), and CXL.
Recognition and awards[edit]
Das Sharma holds more than 160 US patents[7] and more than 400 patents world-wide.[8] He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, various Universities (CMU, Texas A&M, UIUC), and Intel Developer Forum.
Awards[edit]
- 2022 Industrial Pioneer Award by IEEE Circuits and Systems Society[9]
- Lifetime Contribution Award by PCI-SIG in 2022, introduced in 2022[10]
- PCI-SIG Chairman’s award for outstanding contribution, 2022[11]
- 2021 IEEE Region 6 Outstanding Engineer Award[12]
- Distinguished Alumnus Award, IIT, Kharagpur, September 2019[13]
Selected publications[edit]
- D. Das Sharma, "Innovations in Load-Store I/O Causing Profound Changes in Memory, Storage, and Compute Landscape", Storage Developer Conference (SDC), September 2021[14]
- D. Das Sharma, "PCIe 5.0 PHY Logical", PCI-SIG Developers Conference, June 2019[15]
- D. Das Sharma, "PCI Express: What’s Next for Storage", SNIA Storage Developers’ Conference, Santa Clara, Sept 2018.[16]
- D. Das Sharma, "The Evolution of the PCI-Express® Architecture: Going Strong 15 years and Five Generations Later", Embedded Systems Engineering, August 2017[17]
- D. Das Sharma, "PCIe 4.0 PHY Logical", PCI-SIG Developers Conference, June 2015, Santa Clara, CA[18]
- D. Das Sharma, "Intel® 5520 Chipset: An I/O Hub Chipset for Server, Workstation, and High End Desktop", Hot Chips 2009.[19]
- D. Das Sharma, "PCIe 3.0 New Encoding Scheme (PCIe 3.0 Electricals III)", PCI-SIG PCIe Developers’ Conference, June 2008, Santa Clara, CA.[20]
- D. Das Sharma, "PCIe 2.0 Logical Extensions", PCI-SIG PCIe Technology Seminar, Oct 3, 2005, Taipei.[21]
- D. Das Sharma et. al., "TwinCastle: A Multi-processor North Bridge Server Chipset", Hot Chips 2005.[22]
References[edit]
- ↑ "IEEE Xplore Author Bio". ieeexplore.ieee.org. Retrieved 2022-12-08.
- ↑ "IEEE Xplore Author Bio". ieeexplore.ieee.org. Retrieved 2022-12-08.
- ↑ "IEEE Xplore Author Bio". ieeexplore.ieee.org. Retrieved 2022-12-08.
- ↑ "Board of Directors | PCI-SIG". pcisig.com. Retrieved 2022-12-08.
- ↑ "Leadership". Compute Express Link. Retrieved 2022-12-08.
- ↑ "Board Representatives". My Site. Retrieved 2022-12-08.
- ↑ "Debendra Das Sharma Inventions, Patents and Patent Applications - Justia Patents Search". patents.justia.com. Retrieved 2022-12-08.
- ↑ "WIPO - Search International and National Patent Collections". patentscope.wipo.int. Retrieved 2022-12-09.
- ↑ "IEEE Circuits and Systems Society 2022 Awardees | IEEE CASS". ieee-cas.org. Retrieved 2022-12-08.
- ↑ "Lifetime Contribution Award | PCI-SIG". pcisig.com. Retrieved 2022-12-08.
- ↑ "PCI-SIG Chairperson's Award | PCI-SIG". pcisig.com. Retrieved 2022-12-08.
- ↑ Perkins, Ed (2022-03-18). "R6 2021 Awards Ceremony". IEEE Region 6. Retrieved 2022-12-08.
- ↑ Mondal, Poulami (2020-12-15). "Distinguished Alumnus Award Announced for 2020". The KGP Chronicle. Retrieved 2022-12-08.
- ↑ "Innovations in Load-Store I/O Causing Profound Changes in Memory, Storage, and Compute Landscape | SNIA". www.snia.org. Retrieved 2022-12-08.
- ↑ "PCI-SIG - Login". members.pcisig.com. Retrieved 2022-12-08.
- ↑ Coughlin, Tom. "SNIA SDC Dishes Up Storage Innovations". Forbes. Retrieved 2022-12-08.
- ↑ "I'm afraid I can't do that, Dave".
- ↑ "PCI-SIG - Login". members.pcisig.com. Retrieved 2022-12-08.
- ↑ Das Sharma, Debendra (August 2009). "Intel® 5520 chipset: An I / O hub chipset for server, workstation, and high end desktop". 2009 IEEE Hot Chips 21 Symposium (HCS). pp. 1–18. doi:10.1109/HOTCHIPS.2009.7478355. ISBN 978-1-4673-8873-3. Search this book on
- ↑ "PCI-SIG - Login". members.pcisig.com. Retrieved 2022-12-08.
- ↑ "PCI-SIG - Login". members.pcisig.com. Retrieved 2022-12-08.
- ↑ Sharma, Debendra Das; Gupta, Ashish; Kurpanek, Gordon; Mulla, Dean; Pflederer, Bob; Rajamani, Ram (August 2005). "TwinCastle: A multi-processor north bridge server chipset". 2005 IEEE Hot Chips XVII Symposium (HCS). pp. 1–31. doi:10.1109/HOTCHIPS.2005.7476603. ISBN 978-1-4673-8864-1. Unknown parameter
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