ADD (x86 instruction)

In the x86 assembly language, the ADD instruction performs an integer addition on two operands. Flags SF, ZF, PF, CF, OF and AF are modified and the result stored back to the left operand. It can add memory, registers, immediate values and register indirect values. The destination operand can be in memory, in which case a read-modify-write operation is executed in a single instruction and prefix LOCK may be used to force atomic execution. There are 10 different opcodes for the ADD instruction depending on the type and size of the operands. It can add 8-bit, 16-bit, 32-bit or 64-bit valuesTemplate:Cite Intel.

Encoding[edit]

Assembly language[edit]

The ADD instruction has one assembly language format:

ADD ‹destination›,‹source›   ; ‹destination› := ‹destination› + ‹source›

Machine language[edit]

Combined with various prefixes, ten different opcodes (00, 01, 02, 03, 04, 05, 80/0, 81/0, 82/0, 83/0), all introduced with the earliest x86 processor I8086 build up the full functionality of the ADD instruction.

Extensions were introduced with I80386 (32-bit operands) and x86-64 (64-bit operands).

Mnemonic		Opcode				Action	CPU	Notes
Mnemonic		Real mode	16-bit	32-bit	64-bit	Action	CPU	Notes
ADD	b,rb	00 /r				Adds a byte GPR to a byte GPR or memory location	all	^{[lower-alpha 1]}^{[lower-alpha 2]}^{[lower-alpha 3]}
ADD	w,rw	01 /r		66 01 /r		Adds a word GPR to a word GPR or memory location	all	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	d,rd	66 01 /r		01 /r		Adds a double word GPR to a double-word GPR or memory location	I80386+	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	r,rr	N.E.			48 01 /r	Adds a quadword GPR to a quadword GPR or memory location	x86-64	^{[lower-alpha 1]}^{[lower-alpha 4]}
ADD	rb,b	02 /r				Adds a byte GPR or memory location to a byte GPR	all	^{[lower-alpha 2]}^{[lower-alpha 3]}
ADD	rw,w	03 /r		66 03 /r		Adds a word GPR or memory location to a word GPR	all	^{[lower-alpha 2]}
ADD	rd,d	66 03 /r		03 /r		Adds a double word GPR or memory location to a double word GPR	I80386+	^{[lower-alpha 2]}
ADD	rr,r	N.E.			48 03 /r	Adds a quadword GPR or memory location to a quadword GPR	x86-64	^{[lower-alpha 4]}
ADD	b,ib	80 /0 ib				Adds a byte constant to a byte GPR or memory location	all	^{[lower-alpha 1]}^{[lower-alpha 2]}^{[lower-alpha 3]}
ADD	w,iw	81 /0 iw		66 81 /0 iw		Adds a word constant to a word GPR or memory location	all	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	d,id	66 81 /0 id		81 /0 id		Adds a double-word constant to a double-word GPR or memory location	I80386+	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	r,sd	N.E.			48 81 /0 id	Adds a signed-extended double word constant to a quadword GPR or memory location	x86-64	^{[lower-alpha 1]}^{[lower-alpha 4]}
ADD	b,ib	82 /0 ib			N.S.	Adds a byte constant to a byte GPR or memory location	~~x86-64~~	^{[lower-alpha 1]}
ADD	w,sb	83 /0 ib		66 83 /0 ib		Adds a sign-extended byte constant to a word GPR or memory location	all	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	d,sb	66 83 /0 id		83 /0 ib		Adds a sign-extended byte constant to a double word GPR or memory location	I80386+	^{[lower-alpha 1]}^{[lower-alpha 2]}
ADD	r,sb	N.E.			48 83 /0 sb	Adds a sign-extended byte constant to a quadword GPR or memory location	x86-64	^{[lower-alpha 1]}^{[lower-alpha 4]}
ADD	AL,ib	04 ib				Adds a byte constant to the AL register	all
ADD	AX,iw	05 iw		66 05 iw		Adds a word constant to the AX register	all
ADD	EAX,id	66 05 id		05 id		Adds a double word constant to the EAX register	I80386+
ADD	RAX,sd	N.E.			48 05 id	Adds a sign-extended double word constant to the RAX register	x86-64	^{[lower-alpha 5]}

Notations[edit]

In Mnemonics column: Real mode includes Virtual-86, System Management Mode and the unofficial and non-standard Unreal mode; b: byte (8-bit) general-purpose register (GPR) or memory location; rb: byte GPR; ib: byte immediate; sb: byte immediate, sign-extended to operand size; w: word (16-bit) GPR or memory location; rw: word GPR; iw: word immediate; d: double word (32-bit) GPR or memory location; rd: double word GPR; id: double word immediate; sd: double word immediate, sign-extended to 64 bits; r: quadword (64-bit) GPR or memory location; rr : quadword register
In Opcode column: /r: a ModR/M byte follows with bits 3…5 encoding a GPR; /0: a ModR/M byte follows with bits 3…5 equal to 0; ib, iw, id: byte, word or double word immediate follows, always after the memory location offset if present; N.E. : not encodable; N.S. : not supported (opcode reserved, may have been reused)
In CPU column: all: all x86 processors execute this instruction form identically; I80386: this form has been introduced in the I80386 processor; x86-64: this form is executed by a x86-64 processor in 64-bit mode. x86-64 architecture is available if CPUID executed with EAX = 80000001h returns EDX bit 29 = 1Template:Cite Intel; ~~x86-64~~: this form is not supported in 64-bit mode, behaviour is undetermined
In Notes column

↑ ^1.00 ^1.01 ^1.02 ^1.03 ^1.04 ^1.05 ^1.06 ^1.07 ^1.08 ^1.09 ^1.10 ^1.11 If destination is in memory, LOCK prefix is allowed for atomic operation, as well as LOCK+XACQUIRE and LOCK+XRELEASE for hardware lock elision (see Transactional Synchronization Extensions)
↑ ^2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 In 64-bit mode REX prefix (byte values 40…47) immediately before the main opcode is allowed to encode extended registers
↑ ^3.0 ^3.1 ^3.2 If REX prefix used, byte registers AH, BH, CH and DH cannot be encoded. SPL, BPL, SIL and DIL (the lower 8-bits of RSP, RBP, RSI and RDI) are available instead.
↑ ^4.0 ^4.1 ^4.2 ^4.3 The REX.W prefix is mandatory for a 64-bit operation to take place. Other forms (byte values 48…4F) may be used to encode extended registers
↑ The REX.W prefix is mandatory for a 64-bit operation to take place. Other forms have no effect.

Examples[edit]

04 05                   add      al,05              ; add 5 to AL register and store result back to AL
F0 64 83 05 12345678 01 lock add fs:[12345678h],1   ; atomically add 1 to memory address in 12345678 in FS segment
70 05                   jo       $+5                ; jump if OF == 1

Notes[edit]

References[edit]

"Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference, A-M" (PDF). September 2014.

This article "ADD (x86 instruction)" is from Wikipedia. The list of its authors can be seen in its historical. Articles copied from Draft Namespace on Wikipedia could be seen on the Draft Namespace of Wikipedia and not main one.

[lock-1] 1.00 ^1.01 ^1.02 ^1.03 ^1.04 ^1.05 ^1.06 ^1.07 ^1.08 ^1.09 ^1.10 ^1.11 If destination is in memory, LOCK prefix is allowed for atomic operation, as well as LOCK+XACQUIRE and LOCK+XRELEASE for hardware lock elision (see Transactional Synchronization Extensions)

[rex-2] 2.00 ^2.01 ^2.02 ^2.03 ^2.04 ^2.05 ^2.06 ^2.07 ^2.08 ^2.09 ^2.10 In 64-bit mode REX prefix (byte values 40…47) immediately before the main opcode is allowed to encode extended registers

[rex-b-3] 3.0 ^3.1 ^3.2 If REX prefix used, byte registers AH, BH, CH and DH cannot be encoded. SPL, BPL, SIL and DIL (the lower 8-bits of RSP, RBP, RSI and RDI) are available instead.

[rex-w-4] 4.0 ^4.1 ^4.2 ^4.3 The REX.W prefix is mandatory for a 64-bit operation to take place. Other forms (byte values 48…4F) may be used to encode extended registers

[5] The REX.W prefix is mandatory for a 64-bit operation to take place. Other forms have no effect.

[lower-alpha 1]

[lower-alpha 2]

[lower-alpha 3]

[lower-alpha 4]

[lower-alpha 5]