ARM Cortex-X925

ARM Cortex-X925

Produced	2024
Designed by	ARM Ltd.
Instruction set	ARMv9.2-A
Microarchitecture	ARM Cortex-X925
Cores	1–14 per cluster
L1 cache	128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core
L2 cache	2048–3072 KiB per core
L3 cache	512 KiB – 32 MiB (optional)
Address width	40-bit
Predecessor	ARM Cortex-X4
Successor	ARM Cortex-X930
Product code name(s)	Blackhawk
Variant	ARM Cortex-A720

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The Cortex-X925, codenamed "Blackhawk", is a high-performance CPU core designed by Arm and introduced in 2024. It is part of the second-generation ARMv9.2 architecture and is built on a 3 nm process node. The Cortex-X925 is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing.

Key Features

• 10-wide decode and dispatch width: This allows the core to process more instructions per cycle, increasing overall throughput.
• Doubled instruction window size: This reduces stalls and improves the efficiency of the execution pipeline.
• Increased L1 instruction cache (I$) bandwidth: The core features a 2x increase in L1 I$ bandwidth, ensuring quick instruction fetch and decode.
• Enhanced branch prediction unit: Techniques such as folded-out unconditional direct branches reduce mispredicted branches, leading to fewer pipeline flushes and higher sustained IPC.
• Support for ARMv9.2-A instruction set: The core supports A64 instruction set and AArch64 execution state at all exception levels.
• SVE and SVE2: These extensions provide advanced SIMD and floating-point support.
• Error protection: The core includes error protection on L1 instruction and data caches, L2 cache, and MMU Translation Cache (MMU TC) with parity or ECC.

The Cortex-X925 is designed to be used in both homogeneous and heterogeneous DynamIQ™ clusters, providing flexibility in various system configurations.

Released in 2024 as part of Arm's "total compute solution." It serves as the successor of ARM Cortex-X4. X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A725 and/or ARM Cortex-A520 in a System-on-Chip (SoC).

Architecture comparison

uArch	Cortex-A78	Cortex-X1	Cortex-X2	Cortex-X3	Cortex-X4	Cortex-X925	Cortex-X930
Code name	Hercules	Hera	Matterhorn-ELP	Makalu-ELP	Hunter-ELP	Blackhawk	Travis
Architecture	ARMv8.2		ARMv9		ARMv9.2
Peak clock speed	~3.0 GHz			~3.25 GHz	~3.4 GHz	~3.8 GHz	~
Decode Width	4	5		6	10	10
Dispatch	6/cycle	8/cycle			10
Max In-flight	2x160	2x224	2x288	2x320	2x384	2x768
L0 (Mops entries)	1536	3,072		1536	None
L1-I + L1-D	32+32 KiB	64+64 KiB				64+64 KiB
L2	128–512 KiB	256KiB – 1 MiB			0.5 – 2 MiB	0.5 – 3 MiB
L3	0–8 MiB		0–16 MiB		0–32 MiB	0–32 MiB
SVE	None		SVE2

References

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