Comparison of current ARM cores
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This list provides an overview of the properties of ARM-compatible application microprocessor cores. The ARM Cortex-M (microcontrollers) and ARM Cortex-R (real-time) cores aren't included in this table.
Also missing are ARM Cortex-A57, Cortex-A53 and Apple A7 that use the new 64-bit ARMv8-A architecture that is also compatible with the older 32-bit ARMv7 instructions set (for user mode).
Table[edit]
| ARM11 | ARM Cortex-A5 | ARM Cortex-A7 | ARM Cortex-A8 | ARM Cortex-A9 | Qualcomm Scorpion | Qualcomm Krait[1] | ARM Cortex-A15 MPCore | |
|---|---|---|---|---|---|---|---|---|
| Architecture | ARMv6 | ARMv7 | ARMv7 | ARMv7 | ARMv7 | ARMv7 | ARMv7 | ARMv7 |
| Decode | single-issue | single-issue | 2-wide | 2-wide | 2-wide | 2-wide | 3-wide | 3-wide |
| Pipeline depth | 8 stages | 8 stages | 13 stages | 8 stages | 10 stages | 11 stages | 15/17-25 stages | |
| Out-of-order execution | No | No | No | No | Yes | non-speculative[2] | Yes | Yes |
| FPU | VFPv2 | VFPv4 (optional) | VFPv4 | VFPv3 | VFPv3 (optional) | VFPv3 | VFPv4[3] | VFPv4 |
| Pipelined VFP | Yes | Yes | No | Yes | Yes | Yes | Yes | |
| FPU registers | (8 or 32) × 32-bit | 16 × 64-bit | 16 × 64-bit | 32 × 64-bit | (16 or 32) × 64-bit | 32 × 64-bit | ||
| NEON
(SIMD) |
No | 64-bit wide (optional) | 64-bit wide | 64-bit wide | 64-bit wide (optional) | 128-bit wide | 128-bit wide | 128-bit wide |
| Execution ports | 5[4] | 2[5] | 3[6] | 3[1] | 7 | 8[4] | ||
| Process technology | 90/65/45 nm | 40/28 nm | 65/55/45 nm | 65/45/40/32/28 nm | 65/45 nm | 28 nm | 32/28 nm | |
| L0 cache | 4 KB + 4 KB direct mapped | |||||||
| L1 cache | Varying, typically 16 KB + 16 KB | 4-64 KB / core | 8-64 KB / core | 32 KB + 32 KB | 32 KB + 32 KB | 32 KB + 32 KB | 16 KB + 16 KB 4-way set associative | 32 KB + 32 KB per core |
| L2 cache | Varying, typically none | up to 1 MB (optional) | 256 or 512 (typical) KB | 1 MB | 256 KB (Single-core)/512 KB (Dual-core) | 1 MB 8-way set associative (Dual-core)/2 MB (Quad-core) | up to 4 MB per cluster, up to 8 MB per chip | |
| Core configurations | 1-4 | 1, 2, 4 | 1, 2, 4, 8 | 1 | 1, 2, 4 | 1, 2 | 2, 4 | 2, 4, 8 (4×2) |
| Speed per core (DMIPS/MHz) | 1.25 | 1.57 | 1.9 | 2.0 | 2.5 | 2.1 | 3.3 (Krait) / 3.1 (Krait 200) / 3.4 (Krait 300)[7] / 3.6 (Krait 400) | 3.5 |
See also[edit]
References[edit]
- ↑ 1.0 1.1 http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture
- ↑ http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf
- ↑ http://www.anandtech.com/show/5559/qualcomm-snapdragon-s4-krait-performance-preview-msm8960-adreno-225-benchmarks/2
- ↑ 4.0 4.1 "big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7" (PDF). ARM Holdings. Retrieved 6 August 2014.
- ↑ "Cortex-A8_Architecture". Retrieved 6 August 2014.
- ↑ "The ARM Cortex-A9 Processors" (PDF). ARM Holdings. Retrieved 6 August 2014.
- ↑ http://www.linleygroup.com/newsletters/newsletter_detail.php?num=4920
External links[edit]
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