Layerscape

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Layerscape product families are the first of the QorIQ processors to support the Arm instruction set that uses the Layerscape architecture, which is an evolution of the QorIQ processor family from NXP semiconductors (formerly Freescale Semiconductor). The modular Layerscape architecture consists of three independent, scalable layers, allowing NXP to design QorIQ devices with expanded, reduced or removed layers as needed, providing the suitable solution for a given application. LS1 and LS2 families use Cortex A7, A9, A53 and A72 cores.^[1]

LS1 means LS1XXX series (e.g., LS1021A, etc.); LS2 means LS2XXX series. LS2 means a higher performance level than LS1, and it does not indicate a second generation. The middle two digits of the product name are core count; the last digit distinguishes models, with, in most but not all cases, a higher digit meaning greater performance. “A” at the end indicates the Arm processor. LX designates the 16 nm FinFET generation.

The LS1 family is built on the Layerscape architecture is a programmable data-plane engine networking architecture. Both LS1 and LS2 families of processors offer the advanced, high-performance datapath and network peripheral interfaces. These features are frequently required for networking, telecom/datacom, wireless infrastructure, military and aerospace applications.

Initial announcement

Freescale Semiconductor Inc. (acquired by NXP Semiconductors in late 2015) announced a network processor system architecture said to give the flexibility and scalability required by network infrastructure OEMs to handle the market trends of connected devices, massive datasets, tight security, real-time service and increasingly unpredictable network traffic patterns. It modularizes packet acceleration and forwarding operations from high-level routing decisions, streamlines interaction between the layers and utilizes a synchronous run-to-completion model. Layerscape devices also support a consistent programming framework across the architecture using standard C/C++ languages. NXP also announced the first two QorIQ product families based on the Layerscape architecture, the LS1 and LS2. These products included dual Arm Cortex processor cores, virtualization support, advanced security, an array of advanced interconnects, a common ISA and software- and pin-compatibility for simple and smooth application migration between the two families. Targeted applications for the LS1 and LS2 families include residential gateways, enterprise access points, smart energy systems, industrial communications, line cards and robotics.

LS1 Product Family

LS1012A

2 Gbps packet crypto accelerator with a highly power-efficient 64-bit single Arm Cortex-A53 core running up to 1 GHz, and integrated them with a full suite of high speed peripherals. The product incorporates dual 2.5 Gigabit Ethernet, PCIe, SATA3 and USB 3.0 with integrated PHY. The processor can be routed on 4-layer PCBs. It is the smallest and lowest power 64-bit embedded processor in the market (As of Feb 2016). It uses typical power between 1-2 W.

LS1020A

It is one of the first Layerscape products announced by Freescale, along with LS1021A and LS1022A. It has two Arm Cortex-A7 cores running at up to 1 GHz. It is suitable for fanless enterprise and consumer networking applications, such as enterprise access points, multi-protocol IoT gateways and security appliances. It typically uses 2.6 W.

LS1021A

It adds integrated display controller and industrial interfaces for use in factory/building automation, M2M, printing and defense/aerospace applications. The LS1021A processor features two high-efficiency Arm Cortex-A7 cores running up to 1.2 GHz and has error checking and correction (ECC) technology, delivering performance at a typical power of fewer than 3 W.

LS1022A

Cost-optimized version of LS1021A. It has two Arm Cortex-A7 cores running up to 600Mhz.

LS1024A

In April of 2014, Freescale acquired a portion of Mindspeed Technologies (Comcerto Business), which produced Arm-based multicore embedded processors and associated software targeting systems such as home gateways and network-attached storage. Mindspeed had just been acquired by M/A-Com Technology Solutions, and the latter sought to sell off portions of Mindspeed that were not essential to its strategy. Chief among the Mindspeed products is the Comcerto 2000 SoC, which combines two 1.2 GHz Arm Cortex-A9 CPUs with packet engines and communications accelerators. This chip became LS1024A processor of Freescale.

LS1028A

It has two 64-bit Arm Cortex v8 A72 processor cores, an integrated 3D GPU and LCD controller, a four-port time sensitive networking (TSN) switch and two separate TSN Ethernet controllers. By combining time sensitive networking with a GPU, it addresses industrial human machine interface and control applications. It is designed to support both TSN bridging applications as well as TSN endpoint applications and will be offered with a 15-year manufacturing promise. LS1028A is preproduction silicon (As of April 2018).

LS1043A

The SoC, which allows fanless designs, delivers 1.5 GHz of performance and requires power as low as just 6 W to operate. the LS1043A device integrates four 64-bit Arm Cortex-A53 cores, delivering 10+ Gbps and an estimated 16,000+ CoreMarks of CPU performance. The device features advanced virtualization hardware, supports flexible, secure cloud application updates with Freescale’s trust architecture, and offloads latency sensitive applications for optimized local performance with classification and traffic management hardware. It includes 10 GbE plus 5x 1GbE, 3x PCIe, 3x USB 3.0 with PHYs and SATA 3.0.

LS1046A

At the time of the launch, it was the industry's lowest power quad-core Arm Cortex-A72 based devices. It is available in 23 x 23 MM packages and is compatible with LS1023A, LS1043A and LS1088A SoCs. LS1046A offers performance above 32,000 CoreMarks, and integrates 10 GB Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces.

LS1088A

It has eight Arm Cortex-A53 cores running up to 1.5 GHz. It also incorporates DDR4 memory controllers and up to two 10Gb/s and eight 1Gb/s Ethernet interfaces. It is designed for intelligent edge access equipment, NFV and virtual CPE solutions, industrial control systems and intelligent NIC applications.

LA Product Family

In February 2017 NXP announced a new family of fully programmable, multi-standard SoCs for multi-access technologies including 5G evolution. The Layerscape LA family targets scalable solutions in wired and wireless enterprise and carrier networks, and home gateway markets. The family enables rapid deployment of next generation platforms into these markets with fully programmable technology. The architecture offers programmable MAC and PHY layer modem technology. It accommodates multiple modem implementations across Wi-Fi, 5G and other applications.

LA1575

It implements 802.11ax, 802.11ad, and millimeter wave (mmWave) standards on a single SoC device. Initial targets include enterprise and high-end home gateway markets.

LX Product Family

In October of 2017, NXP announced the highest performance member of the Layerscape family, the LX2160A SoC. The LX2160A is specifically designed to enable challenging high-performance network applications, network edge compute, and data center offloads. Trusted and secure execution of virtualized cloud workloads at the edge is driving new distributed computing paradigms.

LX2160A

It features sixteen high-performance Arm Cortex-A72 cores running at over 2 GHz in a sub 30 W power envelope, supporting both the 100 Gbit/s Ethernet and PCIe Gen4 interconnect standards. In addition, it provides L2 switching at wire rate and includes acceleration for data compression and 50 Gbit/s IPSec cryptography.

Layerscape Product Family List

						Security
Device	Cores	Frequency	PCIe	SerDES	SATA	Integrated SEC Engine	DCE/PME	QE
LS1012A	1 x Arm Cortex A53	1.0 GHz	1 x Gen2.0	3 lanes 6 GHz	Yes	Yes	-	-
LS1020A	2 x Arm Cortex A7	1.2 GHz	2 x Gen2.0	4 lanes 6 GHz	Yes	Yes	-	Yes
LS1021A	2 x Arm Cortex A7	1.2 GHz	2 x Gen2.0	4 lanes 6 GHz	Yes	Yes	-	Yes
LS1022A	2 x Arm Cortex A7	0.6 GHz	1 x Gen2.0	1 lane 5 GHz	No	Yes	-	-
LS1024A	2 x Arm Cortex A9	1.2 GHz	2 x Gen2.0	3 lanes 5 GHz	Yes	Yes	Yes	-
LS1028A	2 x Arm Cortex A72	1.3 GHz	2 x Gen2.0	4 lanes 10 GHz	Yes	Yes	-	-
LS1043A	4 x Arm Cortex A53	1.6 GHz	3 x Gen2.0	4 lanes 10 GHz	Yes	Yes	-	Yes
LA1575	2 x Arm Cortex A53	1.4 GHz	1 x Gen3.0	4 lanes 10 GHz	Yes	Yes	-	-
LS1046A	4 x Arm Cortex A72	1.8 GHz	3 x Gen3.0	8 lanes 10 GHz	Yes	Yes	-	-
LS1088A	8 x Arm Cortex A53	1.6 GHz	3 x Gen3.0	4 lanes 10 GHz	Yes	Yes	-	Yes
LX2160A	16 x Arm Cortex A72	2.2 GHz	6x Gen 4.0	24 lanes 25 GHz	Yes	Yes	100 Gbps

References

This article "Layerscape" is from Wikipedia. The list of its authors can be seen in its historical and/or the page Edithistory:Layerscape. Articles copied from Draft Namespace on Wikipedia could be seen on the Draft Namespace of Wikipedia and not main one.

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