List of floppy disk controllers

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This is a list of floppy-disk controllers. It is currently biased towards widely commercially available controllers in the consumer market.

General

References may be in the form of components or nets of a schematic, which will be linked just above those bare references. SH is the sheet number, name/number is a particular pin on a component, nets are usually prefixed by "net" and uppercase or are obviously nets. Active low logic should have either a /slash prefix or a slash/ suffix.

Bare page numbers refer to a service manual cited just above.

List of hidden anchors in this article

FDC	bus	w.p.	PLL	based on	sync
#Micropolis-FDC	S-100		A		/wait
#Morrow-DiskJockey		y	A	WD1791	/wait
#Morrow-DJDMA		?	A	Z80, 82S105	DMA
#CalCompSys-2422		?	?	WD1793	?
#IMSAI8080-FDC		?	?		?
#Altair8800-FDC		?	?		?
#Robotron-K5120	K1520	y	A		/wait
#Vista-A800		?	?	WD1797	?
#Woz_machine					?
#Commodore-1540	serial		D	6502	set ov
#Commodore-2031	IEEE-488		D		?
#Commodore-2040			D	2 × 6502	poll
#Commodore-SFD1		?	A		?
#Commodore-8050, #Commodore-8250		y	A		set ov

Items that require review / further expertise

• #Morrow-DiskJockey PLL theory of operation

Feature description

• Phase-locked loop
  • all floppy disk controllers need a PLL. Information is represented by the presence or absence of a magnetic flux transition at a particular window in time and that flux reversal will generate a pulse. a signal event must happen in that window every time, even if no data pulse is received, first and foremost so that the read shift register can be advanced a step with a zero inserted.
  • digital PLLs are cheap and simple. They consist of a counter clocked by a constant clock. Pulses from the floppy disk drive reset the counter. Since the clock is fixed, variations in motor speed would appear as phase offset errors for each bit (while that phase error would not accumulate)
  • analog PLLs are more complex, but also more precise. A voltage-controlled oscillator is tuned by the difference in phase between the VCO clock and the floppy disk drive pulses. Variations in motor speed result in a different VCO clock frequency and are thus not recurring phase offset errors per bit
• write precompensation
  • a magnetic flux reversal is moved forward or backward by a fraction of the bit time depending on nearby prior or later flux reversals, to compensate for the displacement that will move 2 flux reversals that are very close further apart over time. Unless otherwise noted, the fine-grained displacement of the write signal is achieved with digital circuitry using the base clock that is on the order of 10 times faster than the bit clock and the displacement is thus roughly 10% of the bit time.
• ROM based encoders
  • using ROM chips to lookup MFM clock bits that will be combined with the data bits or to translate data bytes into longer sequences using GCR
• CPU based encoders
  • using software to encode data bits which adds a significant overhead to operations. With real time coding typically being infeasible, this means that such controllers would be prevented from disk accesses for long periods of conversion time compared to more efficient ROM based coders
• simple logic encoders
  • FM abd MFM coding rules are trivial if no exceptions are allowed or needed. therefore a few logic gates suffice to encode.
• shift register
  • the fundamental building block of any floppy controller, either a single register can be used for reading and writing or separate registers can be used for reading and for writing.
• PIO data buffer
  • very few controllers do not have it and the CPU writes directly into the shift register, PIOs are used to buffer a single byte of read data or write data and to provide access to control signals. Typically two PIOs are used.
• /WAIT synchronization
  • quite often found on Z80 based systems. The CPU is halted by the floppy controller for a few clock cycles. Necessary for controllers that do not feature a data buffer. Can also be used to make polling more efficient, i.e. unnecessary.
• polling synchronization
  • a PIO is polled to determine if data can be read or written. This usually requires 2 or 3 instructions in the polling loop
• SET OVERFLOW synchronization
  • a polling method that was slightly more efficient as it only needed a single branch instruction. Used the 6502 set overflow pin. commonly used in Commodore controllers
• DMA transfer
  • a natural companion to a floppy disk controller.
• marker detector
  • wide gate
    • as exemplified by practically all GCR commodore drives, a 10-input NAND gate is used to detect the SYNC marker ("1111111111")
  • ROM based
    • can be found in MFM controllers, since there are a few marker bytes that have to be detected and the combinatorial circuit would have a substantial size
  • per sector index hole
    • not a marker of course, but serves the same function as synchronization markers. The existence of and reliance on an index hole does not imply that no synchronizing markers were used on the disk, as the index hole cannot be precise enough to align to a byte boundary. See for example #Micropolis-FDC.
  • sector 0 index hole
    • rarely used since it implies that either there is only one long sector on each track or that sector markers would have been stored on disk to avoid a ridiculously over-complicated and slow indexing scheme where all access must begin with sector 0. If on-disk markers are used, it is quite irrelevant where the first sector around the circumference of a track starts.
• stepper motor control
  • STP/DIR: since the standard 34-pin floppy drive connector featured a STEP DIRECTION pin and a STEP (pulse) pin, this was very often dictated to floppy controller designers
  • software based: used for example in most commodore controllers which did not use standard connectors between controller and disk drive. software would be responsible for controlling current through the coils of stepper motors during a step sequence
• byte clock / current bit index counter
  • this is just a standard digital counter and there are no variations on the theme, but it is a pivotal part of the controller circuit. the byte clock is reset by sync markers for reading and for writing it is free running and ultimately determines the precise moment where writing starts (in other words, it was not explicitly reset for writing but rather waited out).
• multi-drive controllers and double sided drives
  • connecting multiple disk drives to a single controller was very common. This arrangement implies that only a single head of one drive could be read from or written to at any point in time. concurrent movement of the heads was commonly possible for any number of drives. This is quite interesting: a second drive head could be passing over the disk surface, but it was not used. It was the controller electronics that lacked the sophistication to use floppy disks in true parallel fashion.
• MFM medium data rate convention
  • in MFM if one is to name a clock on whose edges all transitions lie, then this clock would be twice the actual data rate (just as it is in FM mode), but no signal of that frequency can exist under coding rules on the disk. This article uses the nominal frequency (equal to 500khz for a typical 5-inch MFM controller at a data rate of 250kbit/s, but with the actual minimum time between transitions of 4 microseconds and 6 microseconds delay also being possible).
• note (number of tracks)
  • contrary to the bit density per track, the number of tracks per side has no influence on controller design apart from trivial firmware differences to account for the actual geometry. technical improvements that enable a high track density are entirely the domain of the disk drive and the controller just steps in the same way through a now higher number of tracks. In other words, a controller built for a 40-track drive works with a 80-track drive after firmware changes.

Built from only discrete components

• Mircropolis FDC (S-100 bus)
  • schematic no. referenced: 100087 in (February 1979)
  • /WAIT synchronization with no data buffers. the shift register parallel inputs and outputs are directly connected to the system bus (outputs via a bunch of multiplexers to allow read access to status signals), input and output instructions must be started sufficiently early and the completion of these instructions will be delayed by the floppy controller
  • internal 2Mhz crystal or system bus clock
  • FM/MFM selectable requiring a number of jumpers to be changed
  • FM 125kbit/s / 250khz
  • MFM 250bit/s / 500khz
  • MFM coding using simple logic which means IBM style MFM marker bytes that violate MFM coding rules are not possible
  • analog PLL
  • relies on index hole for positioning, preamble of all zero bits (125khz/250khz "tone") to allow PLL lock
    • it actually resets the byte counter during writing on the index hole pulse instead of not caring about a minor offset
  • sector format: 12.5ms; preamble,sync(FF),track,sector,data,check(8bit),postamble (the sync byte is indistinguishable from ordinary data wrt. coding rules)
    • the controller is unaware of those fields, but at the beginning of each sector the read bit counter will be held at value 1 until the first 1 is read from the disk and the bit counter will thus synchronize to the sync byte and the firmware will read the sync byte as the first one of a sector. note that B11 and A12 facilitate aligning the read clock with the correct phase (data) of the clock+data bit window during the preamble.
    • note that standard practice in FM/MFM drives is to have a gap between metadata (with own sync and crc) and data (with own sync and crc)
  • 16 sectors of 256 bytes per track (MFM)
  • used in: Vector Graphic computers
• IMSAI 8080 FDC (S-100) (2 boards)
• Altair 8800 88-DCDD (S-100) (2 boards)
• VEB Robotron K5120
  • schematic no. referenced: 56-330-0202-2 in (December 1984), which is obviously based on the K5120 line of boards, but much easier to read
  • note: all original documentation on this controller and its ecosystem are in german
  • /WAIT synchronization with PIO data buffers
  • internal 10Mhz crystal
  • uses a single 20bit parallel input, parallel output shift register made of 5 chips with 4 bit each.
  • 5-inch FM (125kbit/s), MFM (250kbit/s)
  • 8-inch FM (250kbit/s), MFM (500kbit/s)
  • disk type and modulation software selectable
  • analog PLL, similar to the Micropolis FDC
  • ROM A8:1 for production of MFM clock bits, ROM A8:2 for detection of IBM marker bytes
    • e.g. for MFM: sync: C2, address: A1FE, data: A1FB, deleted data: A1F8, index: C2FC
  • write precompensation
• Woz Machine

Integrated circuits

• NEC uPD765 and clones
  • NEC uPD765
  • Intel 8272
  • VEB Robotron U8272
• Western Digital 1771
  • inverted data bus
  • included features
    • shift register
    • data buffer (1 byte)
    • IBM 3740 marker detector and metadata format compatibility
    • sector and track registers for automatic seek and scan
    • data separator with optional external PLL
    • CRC
    • minimal support for write precompensation: TG43 pin is high when track number is above 42
    • stepper motor control
    • various other control signals
• Western Digital 179x and clones
  • 1791
    • inverted data bus
    • Fujitsu MB8866
    • Fujitsu MB8876 (1791-01, 1791-02)
  • 1793
    • Fujitsu MB8877
  • 1795
    • inverted data bus
    • side select output
  • 1797
    • side select output
• Integrated Woz Machine
• Intel 8271 - an unusual piece of technology: an integrated floppy controller released in 1977 that contained a microprocessor

As part of larger integrated circuits

• Amiga Paula

Controllers based on integrated circuits

• Western Digital 1771
  • TRS-80 Model I expansion interface
• Western Digital 179x
  • WD 1791
    • Morrow Designs Disk Jockey 2D (S-100), manual+schematic
      • schematic no. referenced: "Disk Jockey 2D Revision 4"
      • analog PLL, using ROM 8A as:
        • (facts stated here may be wrong)
        • fe fe fe fe ff ff ff fc fe fe fe fe fe fe fe fe
        • fe fe fe fe fe fe fe fe fe fe fe fe fc fc fc ff
        • explanation of the PLL: if VCO goes high while TRAN and TRAND (delay) are still both high, that is when /VCO which registered TRAN to produce TRAND goes low after the rising edge of /VCO and TRAN is still high then the clock is too fast (0xfc) and charges are removed from the capacitor that maintains the voltage level for the voltage controlled current source that supplies the ring oscillator 4B (less drive current slows down the oscillator). if /VCO is still high (after the rising edge that registered TRAN) and thus TRAND is stil high, but TRAN goes low, the clock is too slow (0xff), charges are added to the oscillator drive and VCO frequency increases. It is not quite clear why the sense is inverted if /DOUBLE=1 (FM) and DDWINDOW=1, but it seems that the PLL is trying to sabotage a lock when DDWINDOW=1 in FM mode.
      • /WAIT synchronization
        • PRDY is held low until the WD1791's DRQ pin goes high (see also 341:302 RLOOP in firmware listing)
  • WD1793
    • California Computer Systems 2422 (S-100) FDC, service manual, schematic
    • Osborne 1
      • part of the main board
      • digital PLL
      • service manual says it is a 1793, but includes the datasheet for the MB8876/MB8877
    • Osborne 1 Executive
      • write precompensation
      • 9216 data separator
    • TRS-80 Model III
      • analog PLL
      • write precompensation (WD2143 four phase clock generator)
      • WD1691 floppy support logic plus 74LS629 VCO
  • WD1797
    • Vista A800 (Apple II)
• WD1771 + WD1791
  • TRS-80 Model I Double Density Adapter Kit
    • analog PLL
    • write precompensation
    • WD1691 floppy support logic plus 74LS629 VCO
    • WD2143 four phase clock generator
    • DDEN controls 1791 CE and 1771 CE and a multiplexer to switch between their DIR,STEP,WD,WG outputs
    • plugs into the 1771 socket on the expansion interface
    • 1771 is supposed to be moved from the expansion interface, so not populated

Controllers that feature a microprocessor

Using only discrete components

• Commodore 2031
  • the only device with IEEE-488 bus that did not have 2 CPUs and used a software GCR coder, it resembles the internal structure of the 1540 controller more than that of any of the other PET controllers, and this resemblance extends to the layout and style of the service manual
• Commodore 1540/1541
  • later PCB revisions replaced some of the standard parts with a Programmable Logic Array / ASIC

Using two microprocessors

• Commodore PET/CBM
  • dual processor
    • all controllers in this group used one of the CPUs to handle the IEEE-488 interface and the high level disk operating system. Communication between the 2 parts of the circuit happened through several static ram chips. Since the clocks of the 2 processors were phase shifted by 180 degrees, this memory was used as a time multiplexed true dual-port ram without the need for additional access synchronization
  • ROM GCR coding
  • variant A
    • digital PLL
    • polling synchronization (these controllers used a 6504 CPU that does not have a set overflow pin)
      • Commodore 2040/3040/4040
  • variant B
    • set overflow synchronization
    • write precompensation
    • analog PLL
    • base clock selectable between 4Mhz and 6Mhz via jumper (TODO: confirm that firmware would have to be updated - given that there was no way for the firmware to learn about the jumper setting if not for a timing analysis of the byte clock it seems very unlikely that the firmware would not have to change), for the standard 6Mhz clock the raw (head) bit rates for the 4 zones are
      • 375khz
      • 400khz
      • 428.57khz
      • 461.54khz
    • Commodore SFD-1001 (single drive)
    • dual drives
    • the digital PCB of these 2 drives was the same (see jumper E3)
      • Commodore 8050 (single head per drive)
      • Commodore 8250 (two heads per drive)

Using programmable logic

• Morrow DJDMA (S-100)
  • Z80 CPU at 4Mhz
  • Signetics 82S105 integrated fuse logic

References

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