TAHOAOS
TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si (TAHOAOS) structure or TE-TAHOS or BE-TAHOS is a type of next generation non-volatile memory that makes it possible to simultaneously improve memory storage density and lifetime of memory device. After first being developed by Y.S. Song and colleagues in 2020.[1], it became one of the promising candidates for enabling hafnium oxide (HfO2) as a charge trapping layer (CTL) with improved retention characteristics. More recently, TAHOAOS structure is utilized in NOR flash technology[2], especially for low power consumption, high memory margin, improved semiconductor reliability, and faster program/erase operation. But, this TAHOAOS method brings inevitable cost increase and fabrication issue, and it is still in developmental stages and further demonstration is needed[3]. It is expected to have advantage over hafnium oxide (HfO2) based future non-volatile memory technology in that it can guarantee substantial durability of memory devices over 10 years and enable stable Triple-Layer Cell (TLC) operation. It can also be classified as next generation non-volatile disk storage.
Description
TAHOAOS structure intelligently adopts specialized tunneling layers with SiO2/Al2O3/SiO2 to resolve intrinsic disadvantage of retention characteristic in HfO2 CTL, meaning that when this specialized tunneling layers are adopted, the physical layer thickness could be intelligently increased while maintaining same equivalent oxide thickness. If this technology is applied after some performance evaluation and thorough quality assurance, it would be a major technological breakthrough in future flash technology, especially for NAND flash and NOR flash. However, this specialized non-volatile memory structure might have limitations that thin film layer of silicon dioxide is hard to be technically deposited directly on hafnium oxide. On top of that, this structure might cause more costs, shorten limited lifetime of fabrication facility, compared to traditional TAHOS technology.
Comparison with traditional memory device structure
Background
Traditionally, the original SONOS (Si/SiO2/Si3N4/SiO2/Si) structure had been most widely used for approximately 30 years, after it was first realized by P.C.Y. Chen of Fairchild Camera and Instrument in 1977[4]. This structure had been often used for application of non-volatile CTF (charge trap flash) memories, such as EEPROM, flash memories, TFT LCD displays. It was distinguished from previous polysilicon-based FG (floating gate) by the use of silicon nitride (Si3N4 or Si9N10) for the charge storage material.
Development
However, according to the increased demand for faster program/erase speed and low power operation, TANOS (TaN/Al2O3/Si3N4/SiO2/Si) structure has been suggested and adopted, recently. The introduction of Al2O3 as a blocking layer in TANOS structure realized the fast program/erase speed and decrease of power consumption. This TANOS structure became mostly adopted memory structure in high performance memory devices. Despite of this advantage of TANOS structure, further improvement is expected to be needed for future memory market due to the rapidly increasing demand of memory market.
Recent efforts
Thereafter, the TAHOS (TaN/Al2O3/HfO2/SiO2/Si) structure is suggested for future memory device structure[5][6]. The HfO2 is used for charge storage material in TAHOS structure, since HfO2 enables storage of information that is 4 times increased compared to previous TANOS structure. But, this TAHOS structure has fundamental weakness of durability, since it does not surely guarantee 10-year warranty on memory device. According to this problem, TAHOAOS structure substitutes the tunneling layers by applying stacked structure of SiO2/Al2O3/SiO2, and enabled 10-year warranty on memory device[1].
References
- ↑ 1.0 1.1 Song, Young Suh; Jang, Taejin; Min, Kyung Kyu; Baek, Myung-Hyun; Yu, Junsu; Kim, Yeonwoo; Lee, Jong-Ho; Park, Byung-Gook (2020-06-01). "Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al2O3/HfO2/SiO2/Al2O3/SiO2/Si structure". Japanese Journal of Applied Physics. 59 (6): 061006. doi:10.35848/1347-4065/ab8275. ISSN 0021-4922.
- ↑ Song, Young Suh; Park, Byung-Gook (March 2021). "Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide". Micromachines. 12 (3): 328. doi:10.3390/mi12030328. PMC 8003636 Check
|pmc=value (help). PMID 33808915 Check|pmid=value (help). - ↑ Congedo, Gabriele; Lamperti, Alessio; Salicio, Olivier; Spiga, Sabina (2012-11-06). "Multi-Layered Al2O3/HfO2/SiO2/Si3N4/SiO2Thin Dielectrics for Charge Trap Memory Applications". ECS Journal of Solid State Science and Technology. 2 (1): N1–N5. doi:10.1149/2.010301jss. ISSN 2162-8769.
- ↑ Chen, P.C.Y. (May 1977). "Threshold-alterable Si-gate MOS devices". IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED...24..584C. doi:10.1109/T-ED.1977.18783. ISSN 1557-9646. Unknown parameter
|s2cid=ignored (help) - ↑ Fu, J.; Singh, N.; Yang, B.; Zhu, C. X.; Lo, G. Q.; Kwong, D. L. (September 2008). "Si-nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si ) nonvolatile memory cell". ESSDERC 2008 - 38th European Solid-State Device Research Conference: 115–118. doi:10.1109/ESSDERC.2008.4681712. Unknown parameter
|s2cid=ignored (help) - ↑ Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G.; Fu, J.; Singh, N.; Lo, G.Q.; Kwong, D.L. (December 2009). "Performance analysis of nonvolatile gate-all-around charge-trapping TAHOS memory cells". 2009 International Semiconductor Device Research Symposium: 1–2. doi:10.1109/ISDRS.2009.5378209. ISBN 978-1-4244-6030-4. Unknown parameter
|s2cid=ignored (help)
Further reading
For further information, please refer to following articles[1][2][3][4][5][6][7]
- ↑ White, M.H.; Adams, D.A.; Bu, J. (July 2000). "On the go with SONOS". IEEE Circuits and Devices Magazine. 16 (4): 22–31. doi:10.1109/101.857747. ISSN 1558-1888.
- ↑ Lue, Hang-Ting; Wang, Szu-Yu; Lai, Erh-Kun; Shih, Yen-Hao; Lai, Sheng-Chih; Yang, Ling-Wu; Chen, Kuang-Chao; Ku, J.; Hsieh, Kuang-Yeu; Liu, R.; Lu, Chih-Yuan (December 2005). "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability". IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.: 547–550. doi:10.1109/IEDM.2005.1609404. ISBN 0-7803-9268-X. Unknown parameter
|s2cid=ignored (help) - ↑ Fu, J.; Singh, N.; Yang, B.; Zhu, C. X.; Lo, G. Q.; Kwong, D. L. (September 2008). "Si-nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si ) nonvolatile memory cell". ESSDERC 2008 - 38th European Solid-State Device Research Conference: 115–118. doi:10.1109/ESSDERC.2008.4681712. Unknown parameter
|s2cid=ignored (help) - ↑ Kang, Chang Yong (2010-01-01). "Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited". Current Applied Physics. 10 (1): e27–e31. Bibcode:2010CAP....10E..27K. doi:10.1016/j.cap.2009.12.007. ISSN 1567-1739.
- ↑ Fu, J.; Singh, N.; Yang, B.; Zhu, C. X.; Lo, G. Q.; Kwong, D. L. (September 2008). "Si-nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si ) nonvolatile memory cell". ESSDERC 2008 - 38th European Solid-State Device Research Conference: 115–118. doi:10.1109/ESSDERC.2008.4681712. Unknown parameter
|s2cid=ignored (help) - ↑ Spiga, Sabina; Congedo, Gabriele; Russo, Ugo; Lamperti, Alessio; Salicio, Olivier; Driussi, Francesco; Vianello, Elisa (September 2010). "Experimental and simulation study of the program efficiency of HfO2 based charge trapping memories". 2010 Proceedings of the European Solid State Device Research Conference: 408–411. doi:10.1109/ESSDERC.2010.5618194. Unknown parameter
|s2cid=ignored (help) - ↑ Fu, J.; Singh, Navab; Zhu, Chunxiang; Lo, Guo-Qiang; Kwong, Dim-Lee (June 2009). "Integration of High-κ Dielectrics and Metal Gate on Gate-All-Around Si-Nanowire-Based Architecture for High-Speed Nonvolatile Charge-Trapping Memory". IEEE Electron Device Letters. 30 (6): 662–664. Bibcode:2009IEDL...30..662F. doi:10.1109/LED.2009.2019254. ISSN 1558-0563. Unknown parameter
|s2cid=ignored (help)
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