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Yiran Chen

From EverybodyWiki Bios & Wiki



Yiran Chen
Yiran ChenYiran Chen 2026.jpg Yiran Chen 2026.jpg
Yiran Chen's Portrait
Native name陈怡然
Born (1976-02-29) February 29, 1976 (age 50)
Zhengzhou, Henan, China
🏫 Education
💼 Occupation
Known for
  • Spintronic and memristive memory technologies
  • Neuromorphic computing
  • Machine learning computing systems (MLSys)
  • Machine Learning for Electronic Design Automation (EDA)
  • Edge computing and edge artificial intelligence (Edge AI)
👩 Spouse(s)Hai "Helen" Li
👶 Children2
🏅 Awards
  • IEEE Council on Electronic Design Automation A. Richard Newton Technical Impact Award (2026)
  • Member of European Academy of Sciences and Arts (2025)
  • NAI Fellow (2023)
  • AAAS Fellow (2022)
  • ACM Fellow (2020)
  • IEEE Fellow (2018)
  • IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2023)
  • IEEE Computer Society Edward J. McCluskey Technical Achievement Award (2022)
🌐 Websiteece.duke.edu/people/yiran-chen/

Yiran Chen (Chinese: 陈怡然; pinyin: Chén Yírán; born February 29, 1976) is a Chinese-born American computer scientist and electrical engineer best known for his contributions to emerging memory technologies and circuits and systems for artificial intelligence (AI). He is currently the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University,[1] where he leads the U.S. National Science Foundation (NSF) AI Institute for Edge Computing Leveraging Next Generation Networks (Athena) and the Institute of AI Engineering (IAIE), and co-leads the Duke Center for Computational Evolutionary Intelligence.

Early life and education

Chen was born in Zhengzhou, Henan, China, into a family of middle-school teachers; his father taught mathematics and his mother taught music.[2] In 1994, he entered the Department of Electronic Engineering at Tsinghua University in Beijing and was later selected for a university-wide accelerated "4+2" program that enrolled 100 students from the 1994 cohort.[2] Chen's future wife, Hai (Helen) Li, was also among the selected participants; they completed their undergraduate education in four years, graduating in 1998.

Chen continued at Tsinghua University to pursue a master's degree[3] under the supervision of Prof. Chongcheng Fan, the first mainland Chinese scientist to be named a Fellow of The Optical Society (OSA, now Optica). He received his M.S. in January 2001.

Chen later joined Purdue University, along with his wife, Hai (Helen) Li, and conducted his doctoral research[4] under the supervision of Profs. Kaushik Roy and Cheng-Kok Koh. During his Ph.D. program, he completed summer internships at Micron Technology in 2002 and 2003. He earned his Ph.D. in the summer of 2005.

Professional career

Industrial career (2005–2010)

Synopsys Inc. (2005–2007)

Chen joined Synopsys Inc. in Silicon Valley in July 2005 as a Senior R&D Engineer, where he developed PrimeTime VX, a statistical static timing analysis tool for modeling the impact of process variations on semiconductor circuit performance.[5][6]

Seagate Technology (2007–2010)

Spintronic Memory. In April 2007, Chen and his wife, Li, joined the newly established Advanced Technology Group (ATG) at Seagate Technology as its first two circuit designers. They focused on developing spintronic memory technologies, which Seagate's leadership viewed as a promising pathway to expanding the company's presence in the emerging storage-class memory (SCM) market. Chen led the design of the first spin-transfer torque random-access memory (STT-RAM) chip fabricated in the United States, demonstrating the technology's feasibility using commercial semiconductor foundry processes.[7][8]

This work built on several of Chen's contributions, including the first integrated electrical–magnetic STT-RAM cell model,[9] self-referenced sensing techniques,[7][8] and variable-write schemes with verification.[10] Together, these innovations provided a comprehensive framework for characterizing and mitigating STT-RAM operational errors arising from device variations and stochastic thermal fluctuations, while significantly reducing memory cell area. This work received multiple Best Paper Awards and nominations.

Based on his STT-RAM cell models and designs, Chen predicted that STT-RAM would become commercially competitive at the 22-nm technology node,[11] particularly as an embedded on-chip memory solution.[12] These predictions, combined with his early experimental demonstrations of STT-RAM, directly led to the inclusion of STT-RAM in the 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).[13] The roadmap recognition helped spur major semiconductor foundries, including TSMC and GlobalFoundries, to invest in the technology and ultimately commercialize their first embedded STT-RAM products at the 22-nm node in 2018.[14][15] His 2008 proposal to use STT-RAM as on-chip memory[12] received the IEEE Council on Electronic Design Automation (CEDA) A. Richard Newton Technical Impact Award in 2026.[16]

Everspin Technologies introduced the first 1-Gb STT-RAM chip in 2019.[17] Today, STT-RAM is widely deployed in mainstream microcontrollers and embedded systems.

Spintronic Memristor. The success of STT-RAM is partly attributable to its unique storage mechanism, in which information is stored as the resistance of a magnetic device. Because this resistance can be programmed and retained, such devices are commonly referred to as "memristors" (memory + resistor). Chen's invention of the "spintronic memristor"[18] in 2009, represents one of the earliest demonstrations of a memristive device and the first memristor based on magnetic phenomena. This work was highlighted in an interview and feature article published by IEEE Spectrum.[19]

Academic career (2010–present)

University of Pittsburgh (2010–2016)

Spintronic Memory (Continued). Chen joined the University of Pittsburgh in Fall 2010 as an Assistant Professor of Electrical and Computer Engineering.[20] There, he continued his research on spintronic memory, publishing on topics including compiler optimizations, memory hierarchy design, multi-level-cell architecture, error-correction techniques, and emerging spintronic memory technologies; several of these papers received Best Paper Awards and nominations.

Neuromorphic Computing and Nonvolatile Memory-based AI Accelerators. In the early 2010s, researchers began exploring the use of memristors to represent synaptic weights for neural network computation. However, progress in this area was limited by the high routing overhead required to interconnect large numbers of memristors. In 2012, Chen, together with Li and researchers from the Air Force Research Laboratory, demonstrated that matrix–vector multiplication—the fundamental operation underlying many modern algorithms—can be efficiently implemented using the crossbar architecture of nonvolatile memories.[21] This design enables all (N X N) element-wise multiplications, where (N) denotes the matrix dimension, to be performed in parallel, thereby achieving the highest computational density attainable with planar semiconductor circuitry. This patented crossbar-array-based analog computing paradigm, later often referred to as a popular computing-in-memory (CiM) technology, has since become the theoretical foundation for numerous AI acceleration chips built on a wide range of nonvolatile memory (NVM) technologies.

In 2014, Chen published two papers that introduced efficient and robust on-chip training[22] and inference[23] schemes for NVM-based neural network accelerators. These works were subsequently recognized with the ASP-DAC 2024 Ten-Year Most Influential Paper Award and the ICCAD 2023 William J. McCalla Ten-Year Retrospective Influential Paper Award, respectively. Building on this foundation, his HPCA 2017 paper[24] proposed the first computing architecture based on the crossbar computing engine introduced in[21], capable of supporting both neural network training and inference.

Chen is a co-inventor of U.S. Patent No. 10,269,406, concerning refresh control for ferroelectric memory.[25]

Machine Learning Computing Systems (MLSys). Toward the end of his tenure at the University of Pittsburgh, Chen began expanding his research focus from nonvolatile memory and AI hardware to the broader area of efficient machine learning computing systems (MLSys). His work emphasized incorporating hardware constraints into AI model design. In 2016, Chen demonstrated that conventional neural network pruning methods, which remove zero or near-zero weights to reduce computational complexity, can in fact degrade performance by disrupting data locality and hardware efficiency. To address this challenge, he introduced structured pruning, a technique that preserves data locality while reducing model complexity.[26] Structured sparsity is supported in machine-learning frameworks and systems including Google TensorFlow, Meta PyTorch, NVIDIA TensorRT, Intel OpenVINO, Apple Core ML, Qualcomm AI Stack, Microsoft DeepSpeed and ONNX Runtime. The paper was ranked by Paper Digest as one of the most influential NeurIPS 2016 papers.[27] In addition, his work on neural network quantization for the IBM TrueNorth chip represents one of the earliest studies on quantization-aware training, demonstrating how hardware implementation constraints can be incorporated into model training to minimize precision requirements while maintaining performance.[28]

Chen was promoted to Associate Professor with tenure at the University of Pittsburgh in 2014.[20][29] He also held a Bicentennial Alumni Faculty Fellowship at Pittsburgh.[20]

Duke University (2017–present)

Chen joined the Department of Electrical and Computer Engineering at Duke University as an Associate Professor in January 2017.

Machine Learning Computing Systems (MLSys) (Continued). During his early years at Duke, Chen extended his quantization research to gradient communication in distributed AI training through his work on TernGrad,[30] a technique that significantly reduces communication overhead by quantizing gradients during distributed learning. TernGrad has since been incorporated into HP products and supported by Facebook Caffe2 and Meta PyTorch. In the same year, Chen proposed the first distributed mobile computing framework for deep neural networks, integrating his innovations in neural network quantization and structured pruning. This work received the Best Paper Award at DATE 2017,[31] and the underlying concept was later adopted by Google in 2019 through the release of TensorFlow Lite, bringing efficient on-device AI inference to a broad range of mobile and edge platforms.

Chen has also worked on the safety, robustness, and privacy of distributed AI systems. His work on privacy-preserving distributed learning ("TIPRDC") received the Best Student Paper Award at KDD 2020.[32] His research on federated prompt tuning for large language models (LLMs) was recognized with the Best Paper Award at the Federated Learning on the Edge Symposium of the AAAI Spring Symposium Series (SSS) 2024.[33] This latter work has since been adopted by NVIDIA's federated learning platform, NVFlare.[34]

Machine Learning for Electronic Design Automation (ML4EDA). Chen has also extended his research on secure and efficient ML systems to the field of electronic design automation (EDA) for semiconductor chip design, specifically machine learning for EDA (ML4EDA). In 2021, he collaborated with Arm Research to develop APOLLO, a technology for accurate runtime power introspection in high-volume commercial microprocessors.[35] This work received the Best Paper Award at MICRO 2021. In 2023, Chen demonstrated that machine learning–based EDA models are highly vulnerable to model extraction attacks when not adequately protected. This work received the Best Paper Award at ASPDAC 2023.[36]

Building on this line of research, Chen's 2024 work introduced the first federated learning framework for ML4EDA, enabling collaborative lithography hotspot detection while preserving data privacy. This work received the Donald O. Pederson Best Paper Award from the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).[37] In addition, at the 2024 International Conference on Machine Learning (ICML), Chen and his co-authors presented LaMAGIC, a language-model-based method for generating analog circuit topologies from design specifications.[38]

Edge AI (Recent). In recent years, building on his broad research portfolio, Chen has focused on edge AI, which seeks to develop an integrated framework for deploying intelligence at the edge across the entire software–hardware stack in an efficient, secure, and scalable manner. In 2021, he received a $20 million grant from the National Science Foundation to launch Athena, the nation's first NSF AI Institute dedicated to edge computing.[39][40]

Teaching and education

At the University of Pittsburgh, Chen launched the School of Engineering's first YouTube channel for embedded systems education,[41] where students present and share their course projects through video demonstrations.

At Duke University, Chen co-developed the course ECE 661: Computer Engineering Machine Learning and Neural Networks. Based on nine offerings of the course, he published the textbook Machine Learning and Neural Networks: A Computer Engineering Perspective[42] with Springer Nature in 2026, together with Hai (Helen) Li and Huanrui Yang.

According to his Duke faculty profile, Chen has supervised or is currently supervising more than 60 doctoral students and four postdoctoral researchers, of whom 14 later joined university faculties.[20]

Chen received the Dean's Award for Excellence in Mentoring from the Duke University Graduate School in 2024.[43]

Leadership and service

Research and institutional centers

In January 2017, Chen co-founded the Duke Center for Computational Evolutionary Intelligence (CEI)[44] and served as its co-Director. The center advances research at the intersection of emerging computing platforms and cognitive applications and has more than 40 affiliated faculty members, postdoctoral researchers, and Ph.D. students.

In September 2018, Chen founded the NSF Industry–University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC),[45] a five-site, multidisciplinary consortium comprising more than 20 industry and government members. The center explores research frontiers in emerging computing platforms for cognitive applications while fostering close collaboration among academia, industry, and government stakeholders.

In October 2021, Chen became the Founding Director and Inaugural Principal Investigator of the NSF AI Institute for Edge Computing Leveraging Next Generation Networks (Athena).[39][40] Athena is one of the 29 national AI institutes established under the United States National AI Research and Development Strategic Plan and serves as the flagship institute of NSF's Computer Systems Research program. The institute supports more than 100 students, researchers, and faculty members across 11 domestic and international universities, advancing foundational research in edge AI, next-generation networking, and intelligent systems.

In 2026, Chen became director of the Institute of AI Engineering at Duke University's Pratt School of Engineering.[46][47]

Professional service and leadership

Chen served as chair of the steering committee of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA).[48]

From January 2020 to December 2023, Chen served as Editor-in-Chief of the IEEE Circuits and Systems Magazine (CAS-M), the flagship publication of the IEEE Circuits and Systems Society.

In February 2024, Chen founded the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), the first IEEE journal dedicated to AI hardware and systems.[49] He has served as its inaugural Editor-in-Chief since its launch.

From July 2021 to June 2024, Chen served as the Chair of ACM's Special Interest Group on Design Automation (SIGDA).[50]

In October 2024, Chen founded the Machine Learning Circuits and Systems (MLCAS) Technical Committee of the IEEE Circuits and Systems Society and served as its inaugural chair until May 2026.

Other activities

From December 2022 to December 2025, Chen served as a member of the Committee on Using Machine Learning in Safety-Critical Applications: Setting a Research Agenda at the National Academies of Sciences, Engineering, and Medicine (NASEM).[51]

In May 2026, Chen co-hosted the National Academy of Engineering Regional Meeting at Duke University, which focused on "Smarter Skies, More Resilient Systems: The Future of Commercial Aviation."[52]

Selected honors and awards

Beyond academia

Business ventures

While pursuing his master's degree at Tsinghua University, Chen and several classmates co-founded the Weilan online bookstore (welan.com).[2]

In 2021, Chinese technology media identified Chen as chairman of NeoNexus Group and a lead founder of its AI chip startup PIMCHIP (苹芯科技), which develops computing-in-memory acceleration units.[60][61]

Chen also serves as a Fellow of Fellows Fund,[62] an AI-focused venture capital firm that invests in Seed and Series A startups, and as an Advisor to Eastlink Capital,[63] a venture capital firm focused on investment opportunities in data infrastructure and AI infrastructure.

Social media

Chen maintains a personal channel[64] on Weibo, one of the largest Chinese-language social media platforms, that focuses on academic research and higher education and has more than 591,000 followers.

Advocacy

Chen is a founding member of the steering committee for the Academic Alliance on AI Policy (AAAIP)[65] and a Fellow of the Asian American Scholar Forum (AASF).[66]

He has commented on artificial intelligence and technology policy in media outlets including Bloomberg,[67] The New York Times,[68][69][70] Reuters,[71] and Channel NewsAsia.

Personal life

Chen is married to Hai (Helen) Li, the Marie Foote Reel E'46 Distinguished Professor and Chair of the Department of Electrical and Computer Engineering at Duke University.[72] They have two sons.[73]

References

  1. ↑ "Duke Awards 44 Distinguished Professorships". Duke Today. May 4, 2023. Retrieved July 21, 2026.
  2. ↑ 2.0 2.1 2.2 "怡"颗清华心 扬帆创未来——访清华电子系1994级校友陈怡然 [Interview with Yiran Chen, Tsinghua Electronic Engineering class of 1994]. Tsinghua Alumni Association (in 中文). March 22, 2021. Archived from the original on July 22, 2026. Retrieved July 21, 2026. Unknown parameter |url-status= ignored (help)
  3. ↑ Master Thesis, Research on Dynamic Property and Gain-Clamping of EDFA, 2000.
  4. ↑ Ph.D. Thesis, Design Techniques for Power Efficiency and Robustness in Scaled High-performance Systems, 2001.
  5. ↑ "Invisible Shield: Technology overview (inventor profile of Yiran Chen)" (PDF). University of Pittsburgh Innovation Institute. Retrieved July 21, 2026.
  6. ↑ "Synopsys Extends PrimeTime and Star-RCXT With Statistical Capabilities To Address Variation-Aware Design Challenges" (Press release). Synopsys. Retrieved July 21, 2026.
  7. ↑ 7.0 7.1 Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, "A 130 nm 1.2V/3.3V 16 Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme," IEEE Journal of Solid-State Circuits (JSSC), vol. 47, no.2, Feb. 2012, pp. 560-573.
  8. ↑ 8.0 8.1 Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2010, pp. 1-6. (Best Paper Award)
  9. ↑ Y. Chen, X. Wang, H. Li, H. Liu and D. Dimitrov, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)," International Symposium on Quality Electronic Design (ISQED), Mar. 2008, pp. 684-690. (Best Paper Award)
  10. ↑ H. Xi, H. Liu, X. Wang, Y. Lu, Y. Chen, Y. Zheng, D. V. Dimitrov, D. Wang, and H. Li, "Variable Write and Read Methods for Resistive Random Access Memory," 7,826,255, 11/02/2010.
  11. ↑ Y. Chen, X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu, "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 18, no. 12, Dec. 2010, pp. 1724-1734.
  12. ↑ 12.0 12.1 X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," ACM/IEEE Design Automation Conference (DAC), Jun. 2008, pp. 554-559.
  13. ↑ https://www.semiconductors.org/wp-content/uploads/2018/08/2013Overview-1.pdf
  14. ↑ https://www.mram-info.com/tsmc-start-emram-production-2018.
  15. ↑ https://investors.gf.com/node/6831/pdf
  16. ↑ 16.0 16.1 "Magnetic Memory: Laying the Foundations for Modern AI". Duke University Pratt School of Engineering. June 29, 2026. Retrieved July 21, 2026.
  17. ↑ "Everspin starts production shipments of its 1Gb STT-MRAM chips". MRAM-Info. December 12, 2019. Retrieved July 21, 2026.
  18. ↑ X. Wang, Y. Chen, H. Xi, H. Li, and D. V. Dimitrov, "Spintronic Memristor through Spin Torque Induced Magnetization Motion," IEEE Electron Device Letters (EDL), Vol. 30, No. 3, pp. 294-297, Mar. 2009.
  19. ↑ https://spectrum.ieee.org/spintronic-memristors.
  20. ↑ 20.0 20.1 20.2 20.3 20.4 "Yiran Chen". Duke Electrical & Computer Engineering. Duke University. Retrieved July 21, 2026.
  21. ↑ 21.0 21.1 M. Hu, H. Li, Q. Wu, G. S. Rose, and Y. Chen, "Memristor Crossbar Based Hardware Realization of BSB Recall Function," International Joint Conference on Neural Networks (IJCNN), Jun. 2012, pp. 1-7.
  22. ↑ B. Li, Y. Wang, Y. Wang, Y. Chen, and H. Yang, "Training Itself: Mixed-signal Training Acceleration for Memristor-based Neural Network," Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2014, pp. 361-366.
  23. ↑ B. Liu, H. Li, Y. Chen, X. Li, T. Huang, Q. Wu, and M. Barnell, "Reduction and IR-drop Compensations Techniques for Reliable Neuromorphic Computing Systems," IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 2014, pp. 63-70.
  24. ↑ L. Song, X. Qian, H. Li, and Y. Chen, "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning," IEEE International Symposium on High-Performance Computer Architecture (HPCA), Feb. 2017, pp. 541-552.
  25. ↑ "US10269406B2: Adaptive refreshing and read voltage control scheme for a memory device such as a FeDRAM". Google Patents. Retrieved July 21, 2026.
  26. ↑ W. Wen, C. Wu, Y. Wang, Y. Chen, and H. Li, "Learning Structured Sparsity in Deep Neural Networks," Annual Conference on Neural Information Processing Systems (NeurIPS), Dec. 2016.
  27. ↑ "Most Influential NIPS Papers (2021-02)". Paper Digest. February 2021. Retrieved July 21, 2026.
  28. ↑ W. Wen, C. Wu, Y. Wang, K. Nixon, Q. Wu, M. Barnell, H. Li, and Y. Chen, "A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip," Design Automation Conference (DAC), June. 2016, Article no. 18.
  29. ↑ "Yiran Chen". IEEE Computer Society. Retrieved July 21, 2026.
  30. ↑ W. Wen, C. Xu, F. Yan, C. Wu, Y. Wang, Y. Chen, and H. Li, "TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning," Annual Conference on Neural Information Processing Systems (NIPS), Dec. 2017.
  31. ↑ J. Mao, X. Chen, K. Nixon, C. Krieger, and Y. Chen, "MoDNN: Local Distributed Mobile Computing System for Deep Neural Network," Design, Automation & Test in Europe (DATE), Mar. 2017, pp. 1396-1401.
  32. ↑ A. Li, Y. Duan, H. Yang, Y. Chen, and J. Yang, "TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations," ACM SIGKDD Conference on Knowledge Discovery and Data Mining (KDD), Aug. 2020, pp. 824-832.
  33. ↑ J. Sun, Z. Xu, H. Yin, D. Yang, D. Xu, Z. Du, Y. Chen, and H. R. Roth, "FedBPT: Efficient Federated Black-box Prompt Tuning for Large Language Models on the Edge," Federated Learning on the Edge Symposium of The AAAI Spring Symposium series (SSS), Mar. 2024.
  34. ↑ https://nvflare.readthedocs.io/en/main/release_notes/flare_280.html
  35. ↑ https://developer.arm.com/community/arm-research/b/articles/posts/fast-power-modelling-for-accurate-cpu-power-introspection
  36. ↑ C.-C. Chang, J. Pan, Z. Xie, J. Hu, and Y. Chen, "Rethink before Releasing your Model: ML Model Extraction Attack in EDA," Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2023, pp. 252-257.
  37. ↑ https://pratt.duke.edu/news/chen-wins-ieee-pederson-award/
  38. ↑ C.-C. Chang, Y. Shen, S. Fan, J. Li, S. Zhang, N. Cao, Y. Chen, and X. Zhang, "LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits," the 41st International Conference on Machine Learning (ICML), PMLR 241:6253-6262, 2024. https://proceedings.mlr.press/v235/chang24c.html
  39. ↑ 39.0 39.1 https://athena.duke.edu/.
  40. ↑ 40.0 40.1 "NSF Launches Artificial Intelligence Research Center at Duke". Duke Today. July 29, 2021. Retrieved July 21, 2026.
  41. ↑ www.youtube.com/user/PittEmbeddedSystem.
  42. ↑ https://link.springer.com/book/10.1007/978-3-032-20979-5.
  43. ↑ https://gradschool.duke.edu/story/2024-deans-award-yiran-chen-phd/.
  44. ↑ https://cei.pratt.duke.edu/.
  45. ↑ https://asic.pratt.duke.edu/.
  46. ↑ "Yiran Chen: Academic Experience". Scholars@Duke. Duke University. Retrieved July 21, 2026.
  47. ↑ Chen, Claire (September 30, 2025). "Pratt considers proposal for new AI engineering institute, undergraduate major". The Duke Chronicle. Retrieved July 21, 2026.
  48. ↑ "Organizing Committee". IEEE Non-Volatile Memory Systems and Applications Symposium 2021. Retrieved July 21, 2026.
  49. ↑ "Chen Named Inaugural Editor-in-Chief of AI-Focused Journal". Duke University Pratt School of Engineering. February 29, 2024. Retrieved July 21, 2026.
  50. ↑ "ACM SIGDA E-Newsletter, July 2021" (PDF). ACM Special Interest Group on Design Automation. July 2021. Retrieved July 21, 2026.
  51. ↑ "Using Machine Learning in Safety-Critical Applications: Setting a Research Agenda". National Academies of Sciences, Engineering, and Medicine. Retrieved July 21, 2026.
  52. ↑ https://pratt.duke.edu/nae-meeting-2026/.
  53. ↑ "2023 NAI Fellows List" (PDF). National Academy of Inventors. December 2023. Retrieved July 21, 2026.
  54. ↑ "Congratulations to the 2023 IEEE CAS Society Award Recipients". IEEE Circuits and Systems Society. Retrieved July 21, 2026.
  55. ↑ "2022 AAAS Fellows". American Association for the Advancement of Science. Retrieved July 21, 2026.
  56. ↑ "Chen Wins IEEE 2022 Edward J. McCluskey Technical Achievement Award". Duke University Pratt School of Engineering. January 27, 2022. Retrieved July 21, 2026.
  57. ↑ "2021 Outstanding Electrical & Computer Engineers". Purdue University Elmore Family School of Electrical and Computer Engineering. Retrieved July 21, 2026.
  58. ↑ "2020 ACM Fellows recognized for work that underpins contemporary computing" (Press release). Association for Computing Machinery. January 13, 2021. Retrieved July 21, 2026 – via GlobeNewswire.
  59. ↑ "Professor Yiran Chen Named IEEE Fellow". Duke Center for Computational Evolutionary Intelligence. November 18, 2017. Retrieved July 21, 2026.
  60. ↑ 杨逍 (August 23, 2021). 36氪首发 | AI芯片公司「苹芯科技」获近千万美元Pre-A轮融资，打造存内计算加速单元 [36Kr exclusive: AI chip company PIMCHIP raises nearly US$10 million in Pre-A funding to build processing-in-memory acceleration units]. 36Kr (in 中文). Retrieved July 21, 2026.
  61. ↑ 明敏 (August 28, 2021). 清华校友陈怡然、杨越组队进军AI芯片市场，成立苹芯科技，最新Pre-A轮斩获近千万美元 [Tsinghua alumni Yiran Chen and Yue Yang team up to enter the AI chip market with PIMCHIP, raising nearly US$10 million in Pre-A funding]. QbitAI (in 中文). Retrieved July 21, 2026.
  62. ↑ https://fellowsfundvc.com/.
  63. ↑ https://www.eastlinkcap.com/team/.
  64. ↑ https://www.weibo.com/u/2199733231.
  65. ↑ https://www.aaaipolicy.org/.
  66. ↑ https://www.aasforum.org/.
  67. ↑ "China's Manus Follows DeepSeek in Challenging US AI Lead," https://www.bloomberg.com/news/articles/2025-03-10/china-s-manus-challenges-us-tech-firms-in-race-to-build-ai-agents, Mar. 10, 2025.
  68. ↑ "What DeepSeek's Success Says About China's Ability to Nurture Talent," https://www.nytimes.com/2025/02/10/world/asia/china-deepseek-education.html, Feb. 10, 2025.
  69. ↑ "China Is Closing the A.I. Gap With the United States," https://www.nytimes.com/2024/07/25/technology/china-open-source-ai.html, Jul. 25, 2024.
  70. ↑ "China's Rush to Dominate A.I. Comes With a Twist," https://www.nytimes.com/2024/02/21/technology/china-united-states-artificial-intelligence.html, Feb. 28, 2024.
  71. ↑ "Pushing the PRAM: when chips just can't get any smaller", https://www.reuters.com/article/technology/pushing-the-pram-when-chips-just-can-t-get-any-smaller-idUSBRE8561CE/, by Jeremy Wagstaff, Reuters, on June 7, 2012.
  72. ↑ "Hai "Helen" Li". Duke Electrical & Computer Engineering. Duke University. Retrieved July 21, 2026.
  73. ↑ "Interview with Dr. Yiran Chen". EDN. Retrieved July 21, 2026.

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