Advanced Performance Extensions: Difference between revisions
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{{distinguish|text = [[iAPX]] (Intel Advanced Performance Architecture)}} | {{distinguish|text = [[iAPX]] (Intel Advanced Performance Architecture)}} | ||
'''Advanced Performance Extensions''' ('''APX'''), also known as '''Intel Advanced Performance Extensions''' ('''Intel APX'''), are extensions to the [[x86]] [[instruction set architecture]] (ISA) for [[microprocessor]]s from [[Intel]].<ref>{{cite web |last1=Robinson |first1=Dan |title=Intel adds fresh x86 and vector instructions for future chips |url=https://www.theregister.com/2023/07/26/intel_x86_vector_instructions/ |website=The Register |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Bonshor |first1=Gavin |title=Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures |url=https://www.anandtech.com/show/18975/intel-unveils-avx10-and-apx-isas-unifying-avx512-for-hybrid-architectures- |website=AnandTech |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Alcorn |first1=Paul |title=Intel's New AVX10 Brings AVX-512 Capabilities to E-Cores |url=https://www.tomshardware.com/news/intels-new-avx10-brings-avx-512-capabilities-to-e-cores |website=Tom's Hardware |date=24 July 2023 |access-date=22 October 2023}}</ref> Called "generational"<ref>{{cite web |last1=Shah |first1=Agam |title=Intel's Generational On-Chip Change APX Will Make All the Apps Faster |url=https://thenewstack.io/intels-generational-on-chip-change-apx-will-make-all-the-apps-faster/ |website=The New Stack |date=9 August 2023 |access-date=22 October 2023}}</ref> and "the biggest x86 addition since 64 bits",<ref>{{cite web |last1=Byrne |first1=Joseph |title=APX is Biggest x86 Addition Since 64 Bits |url=https://www.techinsights.com/blog/apx-biggest-x86-addition-64-bits |website=Tech Insights}}</ref> the improvements double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.<ref>{{Cite web |last1=Winkel |first1=Sebastian |last2=Agron |first2=Jason |title=Advanced Performance Extensions (APX) |url=https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html |access-date=2023-10-22 |website= | '''Advanced Performance Extensions''' ('''APX'''), also known as '''Intel Advanced Performance Extensions''' ('''Intel APX'''), are extensions to the [[x86]] [[instruction set architecture]] (ISA) for [[microprocessor]]s from [[Intel]].<ref>{{cite web |last1=Robinson |first1=Dan |title=Intel adds fresh x86 and vector instructions for future chips |url=https://www.theregister.com/2023/07/26/intel_x86_vector_instructions/ |website=The Register |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Bonshor |first1=Gavin |title=Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures |url=https://www.anandtech.com/show/18975/intel-unveils-avx10-and-apx-isas-unifying-avx512-for-hybrid-architectures- |website=AnandTech |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Alcorn |first1=Paul |title=Intel's New AVX10 Brings AVX-512 Capabilities to E-Cores |url=https://www.tomshardware.com/news/intels-new-avx10-brings-avx-512-capabilities-to-e-cores |website=Tom's Hardware |date=24 July 2023 |access-date=22 October 2023}}</ref> Called "generational"<ref>{{cite web |last1=Shah |first1=Agam |title=Intel's Generational On-Chip Change APX Will Make All the Apps Faster |url=https://thenewstack.io/intels-generational-on-chip-change-apx-will-make-all-the-apps-faster/ |website=The New Stack |date=9 August 2023 |access-date=22 October 2023}}</ref> and "the biggest x86 addition since 64 bits",<ref>{{cite web |last1=Byrne |first1=Joseph |title=APX is Biggest x86 Addition Since 64 Bits |url=https://www.techinsights.com/blog/apx-biggest-x86-addition-64-bits |website=Tech Insights}}</ref> the improvements double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.<ref>{{Cite web |last1=Winkel |first1=Sebastian |last2=Agron |first2=Jason |title=Advanced Performance Extensions (APX) |url=https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html |access-date=2023-10-22 |website=Intel |language=en}}</ref> | ||
Intel contributed APX support to [[GNU Compiler Collection]] (GCC) 14.<ref>{{cite web |last1=Larabel |first1=Michael |title=Intel APX Code Begins Landing Within The GCC Compiler |url=https://www.phoronix.com/news/GCC-Intel-APX-Starts-Landing |website=Phoronix |access-date=22 October 2023}}</ref> Support is also in [[GNU Binutils]] 2.42. | Intel contributed APX support to [[GNU Compiler Collection]] (GCC) 14.<ref>{{cite web |last1=Larabel |first1=Michael |title=Intel APX Code Begins Landing Within The GCC Compiler |url=https://www.phoronix.com/news/GCC-Intel-APX-Starts-Landing |website=Phoronix |access-date=22 October 2023}}</ref> Support is also in [[GNU Binutils]] 2.42. | ||
Revision as of 07:07, 1 December 2024
Advanced Performance Extensions (APX), also known as Intel Advanced Performance Extensions (Intel APX), are extensions to the x86 instruction set architecture (ISA) for microprocessors from Intel.[1][2][3] Called "generational"[4] and "the biggest x86 addition since 64 bits",[5] the improvements double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.[6]
Intel contributed APX support to GNU Compiler Collection (GCC) 14.[7] Support is also in GNU Binutils 2.42.
Extensions
According to the architecture specification,[8] the main features of APX follow:
- 16 additional general-purpose registers, called the Extended GPRs (EGPRs)
- Three-operand instruction formats for many integer instructions
- New conditional instructions for loads, stores, and comparisons with common instructions that don't modify flags
- Optimized register save/restore operations
- A 64-bit absolute direct jump instruction
Extended GPRs for general purpose instructions are encoded using 2-byte REX2 prefix, while new instructions and extended operands for existing AVX/AVX2/AVX-512 instructions are encoded with extended EVEX prefix which has four variants used for different groups of instructions.
References
- ↑ Robinson, Dan. "Intel adds fresh x86 and vector instructions for future chips". The Register. Retrieved 22 October 2023.
- ↑ Bonshor, Gavin. "Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures". AnandTech. Retrieved 22 October 2023.
- ↑ Alcorn, Paul (24 July 2023). "Intel's New AVX10 Brings AVX-512 Capabilities to E-Cores". Tom's Hardware. Retrieved 22 October 2023.
- ↑ Shah, Agam (9 August 2023). "Intel's Generational On-Chip Change APX Will Make All the Apps Faster". The New Stack. Retrieved 22 October 2023.
- ↑ Byrne, Joseph. "APX is Biggest x86 Addition Since 64 Bits". Tech Insights.
- ↑ Winkel, Sebastian; Agron, Jason. "Advanced Performance Extensions (APX)". Intel. Retrieved 2023-10-22.
- ↑ Larabel, Michael. "Intel APX Code Begins Landing Within The GCC Compiler". Phoronix. Retrieved 22 October 2023.
- ↑ "Intel® Advanced Performance Extensions (Intel® APX) Architecture Specification". Intel. 2023-07-21. Retrieved 2023-10-22.
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