Bit manipulation instruction set
Bit manipulation instruction sets perform bit manipulation in hardware, as single instructions, rather than several as illustrated with examples in software.[1] Several leading as well as historic architectures have bitmanipulation instructions including ARM, WDC 65C02, the TX-2 and the Power ISA.[2]
Bitmanipulation is usually divided into subsets as individual instructions can be costly to implement in hardware when the target application has no justification. Conversely, if there is a justification then performance may suffer if the instruction is excluded. Carrying out the cost-benefit analysis is a complex task: one of the most comprehensive efforts in Bitmanipulation was a collaboration headed by Clare Wolfe, providing justifications, use-cases, c code, proofs and Verilog for each proposed instruction.[3][4]
Particular practical examples include Bit banging of GPIO using a low-cost Embedded controller such as the WDC 65C02, 8051 and Atmel PIC. At the slow clock rate of these CPUs, if bit-set/clear/test bitmanipulation were not available the use of that low-cost CPU would not be possible for the target application.
Hardware bitmanipulation
All the architectures below have instruction subsets and groups where the bitmanipulation is provided in hardware.
Intel and AMD (x86)
- For Intel and AMD bitmanipulation instructions see X86 Bit manipulation instruction set
- The AVX-512 extension includes a Bitwise ternary logic instruction,
vpternlog. - The 8086 has
TEST, as well as bitwise operations[5] - The 8051 has
SETB,CLRandCPL- set clear and invert bit instructions - and a considerable number of bitmanipulation instructions.[6] Also included is Or-complement and And-complement, present in RISC-V Zb*.[7]
Power ISA
Power ISA has a large range of bit manipulation instructions,[8] largely due to its history and relationship with IBM mainframes and the z/Architecture:
- Popcount
- Count leading zeros
- bit-extract and bit-deposit
- 8x8 bit permute (
bpermd) - Ternary 8-bit Bitwise ternary logic instruction
xxeval[9] similar to AVX-512 - SWAR-style 8, 16 and 32-bit parity instructions
- bit-matrix multiply and transpose, which are computationally otherwise very expensive.
- strategic instructions for accelerating Packed BCD.
- Power v3.1 also introduced a number of additional bitmanipulation instructions including swapping the order of bytes within half-words, words, and the whole 64-bit register.
z-Architecture
IBM z/Architecture has both scalar and vector processor bitmanipulation instructions. Scalar includes:
- And-complement and others,
- bit-extract and deposit,[10]
- popcount,[11]
- count leading and trailing zeros,[12]
- a range of bit byte and masked insert instructions,[13],
- comprehensive rotate and insert instructions including masked rotate-and-OR,[14] and shift,[15]
- comprehensive Packed BCD.[16]
- memory-based test-and-set and various masked-test set/clear bit operations, which move or copy a single bit into Condition Codes.[17]
Vector includes:
- Vector count-leading zeros
vclz, trailingvctz[18] andvpopct[19] - Vector test under mask
vtm[20] - sets a Condition Code based on comparing all elements of one register against a second vector as a mask: if all masked-comparisons are all-zero, if all are all-ones or a mix of both. - Vector GF(2) multiply and multiply-accumulate,
vgfm[21], known as Carryless multiply
ARM
- ARM11 has bitwise test-ANDed (a bitmasked test) and test-XOR, standard logical bitwise operations including OR-complement; byte halfword and bit-reversing, and conditional byte-selection/merging. Shift and rotate are available on Operand2.[22]
- ARM Cortex-A has bit-field set, clear, extract and reverse.[23]
- ARM A64 has SWAR-style half-word byte-swapping, bit-field insert and extract, and bit-reversing.[24]
RISC-V
In the standard extensions RISC-V has scalar bitwise operations including shift and arithmetic shift, but no rotate. The omissions are compensated for with additional extensions.
- RISC-V Zb* extensions contain a significant number of bitmanipulation instructions.[25] The four groups are broken down into useful categories (the integer subset has min/max, rotate and Popcount for example), and have very good researched justifications for their inclusion and the improvements they bring.[26]
- The RISC-V Vector Extension (RVV) has instructions that qualify as hardware-level bitmanipulation, but on Vector masks rather than Scalar registers as is normally the case. For example, a Vector-mask Popcount is available.[27] RVV also has per-element bitwise operations.[28]
MOS 6502
- The WDC 65C02 added bit-manipulation: set, reset and test on individual bits.
- Rockwell added similar extensions (RMB, SMB, BBR and BBS) to the R65C00 series[29]
others
- Texas Instruments DSPs such as the TMS320C6000 series have set, clear, invert, test, extract and insert bit (or bit-field) instructions.[30]
- The TX-2 from 1958 had "skip on bit" predication, as well as set, clear, invert and permute bits, and shift and other bitwise operations.[31][32]
- The Atmel PIC range also has bitwise operations and set, clear and test bit, listed in the instructions.
See also
References
- z/Architecture Principles of Operation (PDF) (Fifteenth ed.). IBM. April 2025. SA22-7832-14. Retrieved July 3, 2025. Search this book on
- Power ISA™ Version 3.1 (PDF) (v3.1 ed.). IBM. May 1, 2020. SA22-7832-14. Retrieved Aug 7, 2025. Search this book on
- ↑ "Bit Twiddling Hacks".
- ↑ "Advanced bit manipulation instructions: Architecture, implementation and applications". ProQuest.
- ↑ https://github.com/riscv/riscv-bitmanip/tree/v0.93
- ↑ https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf
- ↑ "Bit Manipulation Instructions in 8086 | Logical Instructions". 11 August 2018.
- ↑ https://cs.uok.edu.in/Files/79755f07-9550-4aeb-bd6f-5d802d56b46d/Custom/InstructionSet_UnitII.pdf
- ↑ "Boolean (Bitwise) instructions in 8051 for bit manipulation". 29 April 2020.
- ↑ power3.1 & IBM Power ISA v3.1.
- ↑ power3.1, pp. Power ISA Book I Chapter 7. Vector-Scalar Extension Facility p967.
- ↑ z, pp. 7/36.
- ↑ z, pp. 7/424.
- ↑ z, pp. 7/289-290.
- ↑ z, pp. 7/309.
- ↑ z, pp. 7/426-430.
- ↑ z, pp. 7/437.
- ↑ z, pp. 8/1-8/14.
- ↑ z, pp. 7/458-459.
- ↑ z, pp. 22/11 – 22/12.
- ↑ z, pp. 22/26.
- ↑ z, pp. 22/37.
- ↑ z, pp. 22/16.
- ↑ https://pages.cs.wisc.edu/~markhill/restricted/arm_isa_quick_reference.pdf
- ↑ "Documentation – Arm Developer".
- ↑ "Documentation – Arm Developer".
- ↑ "Riscv-bitmanip/Bitmanip/Index.adoc at main · riscv/Riscv-bitmanip". GitHub.
- ↑ "Riscv-bitmanip/Bitmanip/Overview.adoc at main · riscv/Riscv-bitmanip". GitHub.
- ↑ "Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec". GitHub.
- ↑ "Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec". GitHub.
- ↑ "Rockwell R6500/11, R6500/12 and R6500/15 One-Chip Microcomputers". 7 Jun 1987. Archived from the original on 4 August 2020. Retrieved 30 Apr 2020. Unknown parameter
|url-status=ignored (help) - ↑ https://www.ti.com/lit/pdf/spru198
- ↑ "TX-2 Documentation".
- ↑ http://www.bitsavers.org/pdf/mit/tx-2/TX-2_UserHandbook_ch3.pdf
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