CAST-32A
| Latest version | A November 2016 |
|---|---|
| Organization | FAA |
| Domain | Aviation |
| Abbreviation | CAST-32A |
| Website | faa.gov |
Search CAST-32A on Amazon.
CAST-32A, Multi-core Processors is a position paper,[1] by a Certification Authorities Software Team (CAST). It is not official guidance, but considered informational by certification authorities such as the FAA and EASA. A key point is that multicore "interference can affect execution timing behavior, including worst case execution time (WCET)."[2]
The original document was published in 2014 by an "an international group of certification and regulatory authority representatives."[3] The current revision A was released in 2016. "The Federal Aviation Administration (FAA) and European Aviation Safety Agency (EASA) worked with industry to quantify a set of requirements and guidance that should be met to certify and use multi-core processors in civil aviation, described e.g. in the FAA CAST-32A Position Paper and the EASA Use of MULticore proCessORs in airborne Systems (MULCORS) research report."[4] An Advisory Circular (AC) that formalizes guidance for multicore systems and harmonizes guidance between FAA and EASA is expected in late 2020.[5]
One of the first mixed-criticality multicore avionics systems is expected to be certified sometime in 2020[6]. The objectives of the standard are applicable to software on multicore processors, including the operating system[7], [8]. However, the nature of the underlying processor hardware must examined in detail to identify potential interference channels due to inter-core contention for shared resources[9]. Verification that multicore interference channels have been mitigated can be accomplished through the use of interference generators, i.e., software tuned to create a heavy usage pattern on a shared resource[10]. By creating stress on the shared resource, the impact of contention between cores can be measured and quantified.
Objectives[edit]
The standard presents nine objectives that must be met, depending on the Design Assurance Level (DAL).[1]
| Objective | Applicable Design Assurance Levels |
|---|---|
| MCP Planning 1 | A, B, C |
| MCP Resource Usage 1 | A, B, C |
| MCP Resource Usage 2 | A, B |
| MCP Planning 2 | A, B, C |
| MCP Resource Usage 3 | A, B |
| MCP Resource Usage 4 | A, B |
| MCP Software 1 | A, B, C |
| MCP Software 2 | A, B, C |
| MCP Error Handling 1 | A, B |
| MCP Accomplishment Summary 1 | A, B, C |
References[edit]
- ↑ 1.0 1.1 "Multi-core Processors" (PDF). CAST-32A. Federal Aviation Administration. 2016-11-01. Retrieved 2020-03-23.
- ↑ VanderLeest, Steven H.; Evripidou, Christos (2020-03-10). "An Approach to Verification of Interference Concerns for Multicore Systems (CAST-32A)". SAE International. Retrieved 2020-03-11.
- ↑ Kuhhlert, Oliver (2020-02-11). "Multi-Core Ready to Become Airborne". Embeded Computing Design.
- ↑ Athavale, Jyotika; Mariani, Riccardo; Paulitsch, Michael (2019-03-19). "Flight Safety Certification Implications for Complex Multi-Core Processor Based Avionics Systems". 2019 IEEE International Reliability Physics Symposium (IRPS). IEEE: 1–6. doi:10.1109/IRPS.2019.8720422. ISBN 978-1-5386-9504-3. Unknown parameter
|s2cid=ignored (help) - ↑ Wolfe, Frank (2020-02-28). "EASA and FAA to Issue Further Guidance on Multicore Certification This Year". Avionics International. Retrieved 2020-03-09.
- ↑ Radack, David; Tiedeman, Jr., Harold G.; Parkinson, Paul (2018). "Civil Certification of Multi-core Processing Systems in Commercial Avionics". Rockwell Collins. Retrieved 2020-03-23.
- ↑ "DDC-I and Rapita Systems Simplify Verification and Certification of Multicore Avionics Applications". 2020-04-21. Retrieved 2020-03-23.
- ↑ Brown, Mark (2018-11-15). "CAST=32A: Significance and Implications". Retrieved 2020-12-11.
- ↑ Agirre, Irune; Abella, Jaume; Azkarate-askasua, Mikel; Cazorla, Francisco (2017-06-14). "On the Tailoring of CAST-32A CertificationGuidance to Real COTS Multicore Architectures". IEEE. Retrieved 2020-03-23.
- ↑ VanderLeest, Steven H.; Evripidou, Christos (2020-03-10). "An Approach to Verification of Interference Concerns for Multicore Systems". SAE. Retrieved 2020-03-23.
Category:RTCA standards Category:Computer standards Category:Avionics Category:Safety engineering Category:Embedded systems Category:Software requirements Script error: No such module "AfC submission catcheck".
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