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Intellitech Corp.

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Intellitech Corp.
Software development
Founded 📆1988; 33 years ago (1988) in Dover, New Hampshire
Founder 👔
Headquarters 🏙️,
Dover, New Hampshire
Area served 🗺️
Key people
C.J. Clark (CEO)
Revenue$43.2 million[1]
Number of employees
216 (2018)

Intellitech Corp. is an electronic design automation (EDA) software company. It is headquartered in Dover, New Hampshire[2] with a development office in Bangalore, India and sales/support offices in Mountain View, California, Ottawa (Canada), and Munich, Germany.[3] The company was incorporated in the US in 1988 and is privately held.[3] Intellitech Corporation owns the trademark "Intellitech" in the US, EU and other countries.[3]

Electronics development[edit]

Intellitech develops an integrated solution of application software, soft IP and integrated circuits that lower the cost of deploying electronic products.[4] For example, to test more JTAG-based circuits at a time, the company has patented a technique called "Concurrent JTAG" enabling simultaneous test of multiple targets over JTAG (IEEE 1149.1) without incurring the penalty of longer JTAG shifting sequences.[5][6] To enable PCB self-test, the company has patented self-contained on-board JTAG BIST.[7]


In 2004, Test & Measurement World magazine awarded Intellitech's PT100 parallel tester the Best in Test Award.[8]

In 2011, Intellitech's software Nebula was voted in the top 5 list of design for test and boundary scan software by EDN magazine.[9]

See also[edit]

  • List of EDA companies


  1. "Intellitech Corporation". ZoomInfo.com. 2019-03-05. Retrieved 2019-03-05.
  2. "Intellitech Corp. - Company Profile", Goliath/ECNext, March 2008, webpage: Intellitech-Corp.
  3. 3.0 3.1 3.2 "Intellitech Corporation - Company Overview", Intellitech website, 2008, webpage: Intellitech-company.
  4. "IEEE 1149.1-2013 Enables Integrated Circuit Counterfeit Protection". IEEE-USA InSight. Retrieved 2019-03-05.
  5. "IEEE Standard for Test Access Port and Boundary-Scan Architecture". IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001). 2013-05-01. pp. 1–444. doi:10.1109/IEEESTD.2013.6515989. Retrieved 2019-03-06.
  6. "IEEE 1149.1-2013 - IEEE Standard for Test Access Port and Boundary-Scan Architecture". standards.ieee.org. Retrieved 2019-03-06.
  7. "Chip Design » Managing Multiple Bitstream Images for Format Agile Applications by Managing Multiple Bitstream Images for Format Agile Applications". chipdesignmag.com. 2009-08-24. Retrieved 2019-03-05.
  8. "Test & Measurement World - T&MW Announces Award Winners". www.reed-electronics.com. Retrieved 2019-03-05.
  9. Sargent, D. "Best in Test Finalists 2011: Design for test and boundary scan". EDN. Retrieved 2019-03-05.

External links[edit]

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