List of discontinued x86 instructions
Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.
Intel instructions[edit]
Intel 80386 instructions[edit]
The following instructions were introduced in the Intel 80386, but later discontinued:
| Description | Instruction | Opcode | Eventual fate |
|---|---|---|---|
| Extract Bit String | XBTS r,r/m | 0F A6 /r | Discontinued from revision B1 of the 80386 onwards. |
| Insert Bit String | IBTS r/m, r | 0F A7 /r | |
| Move from test register | MOV TRx,r32 | 0F 24 /r | Present in 80486 and some later Cyrix CPUs. Not present in Pentium or any later Intel CPUs. |
| Move to test register | MOV r32,TRx | 0F 26 /r |
Intel Itanium instructions[edit]
These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation.
| Instruction | Opcode | Meaning |
|---|---|---|
| JMPE r/m16/32 | 0F 00 /6 | Jump To Intel Itanium Instruction Set.[1] |
| JMPE disp16/32 | 0F B8 rel16/32 |
Intel MPX instructions[edit]
These instructions where introduced in Intel "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPU.
Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.
| Instruction | Opcode | Description | Notes |
|---|---|---|---|
| BMDMK b,m | F3 0F 1B /r | Make lower and upper bound from memory address expression. | The lower bound is given by base component of address, the upper bound by 1-s complement of the address as a whole. Using RIP-relative addressing not permitted (results in #UD) |
| BNDCL b, r/m | F3 0F 1A /r | Check address against lower bound. | Produces a #BR exception if the bounds check fails. |
| BNDCU b, r/m | F2 0F 1A /r | Check address against upper bound in 1's-complement form | |
| BNDCN b, r/m | F2 0F 1B /r | Check address against upper bound | |
| BMDMOV b, b/m | 66 0F 1A /r | Move a pair of memory bounds to/from memory or between bounds-registers | |
| BNDMOV b/m, b | 66 0F 1B /r | ||
| BNDLDX b,mib | 0F 1A /r | Load bounds from the bounds-table, using address translation using an sib-addressing expression mib | Requires memory addressing modes that use the SIB byte.
Produces a #BR exception if bounds directory entry is not valid (which prevents address translation). |
| BNDSTX mib,b | 0F 1B /r | Store bounds into the bounds-table, using address translation using an sib-addressing expression mib | |
| BND | F2 | Instruction prefix used with certain branch instructions to indicate that they should not clear the bounds registers. | If the BNDPRESERVE config bit is not set, then branches without this prefix will clear all four bounds registers. |
Intel Xeon Phi "Knights Corner" instructions[edit]
The first generation Xeon Phi processors, codenamed "Knights Corner", supported a large number of instructions that are not seen in any later x86 processor. An instruction reference can be found at [1]. Most of these instructions are similar but not identical to instructions in AVX-512 - later Xeon Phi processors replaced these instructions with AVX-512.
AMD instructions[edit]
3DNow! instructions[edit]
Added with K6-2
| Instruction | Opcode | Meaning |
|---|---|---|
| FEMMS | 0F 0E | Faster Enter/Exit of the MMX or floating-point state |
| PAVGUSB mm1, mm2/m64 | 0F 0F /r BF | Average of unsigned packed 8-bit values |
| PF2ID mm1, mm2/m64 | 0F 0F /r 1D | Converts packed floating-point operand to packed 32-bit integer |
| PFACC mm1, mm2/m64 | 0F 0F /r AE | Floating-point accumulate |
| PFADD mm1, mm2/m64 | 0F 0F /r 9E | Packed, floating-point addition |
| PFCMPEQ mm1, mm2/m64 | 0F 0F /r B0 | Packed floating-point comparison, equal to |
| PFCMPGE mm1, mm2/m64 | 0F 0F /r 90 | Packed floating-point comparison, greater than or equal to |
| PFCMPGT mm1, mm2/m64 | 0F 0F /r A0 | Packed floating-point comparison, greater than |
| PFMAX mm1, mm2/m64 | 0F 0F /r A4 | Packed floating-point maximum |
| PFMIN mm1, mm2/m64 | 0F 0F /r 94 | Packed floating-point minimum |
| PFMUL mm1, mm2/m64 | 0F 0F /r B4 | Packed floating-point multiplication |
| PFRCP mm1, mm2/m64 | 0F 0F /r 96 | Floating-point reciprocal approximation |
| PFRCPIT1 mm1, mm2/m64 | 0F 0F /r A6 | Packed floating-point reciprocal, first iteration step |
| PFRCPIT2 mm1, mm2/m64 | 0F 0F /r B6 | Packed floating-point reciprocal/reciprocal square root, second iteration step |
| PFRSQIT1 mm1, mm2/m64 | 0F 0F /r A7 | Packed floating-point reciprocal square root, first iteration step |
| PFRSQRT mm1, mm2/m64 | 0F 0F /r 97 | Floating-point reciprocal square root approximation |
| PFSUB mm1, mm2/m64 | 0F 0F /r 9A | Packed floating-point subtraction |
| PFSUBR mm1, mm2/m64 | 0F 0F /r AA | Packed floating-point reverse subtraction |
| PI2FD mm1, mm2/m64 | 0F 0F /r 0D | Packed 32-bit integer to floating-point conversion |
| PMULHRW mm1, mm2/m64 | 0F 0F /r B7 | Multiply signed packed 16-bit values with rounding and store the high 16 bits |
| PREFETCH m8 | 0F 0D /0 | Prefetch processor cache line into L1 data cache |
| PREFETCHW m8 | 0F 0D /1 | Prefetch processor cache line into L1 data cache with intent to write.
The PREFETCHW instruction is also supported on Intel CPUs starting with 65 nm Pentium 4,[2] albeit executed as NOP until Broadwell. |
3DNow+ instructions added with Athlon and K6-2+[edit]
| Instruction | Opcode | Meaning | Notes |
|---|---|---|---|
| PF2IW mm1, mm2/m64 | 0F 0F /r 1C | Packed Floating-point to 16-bit Integer Conversion | Also present as undocumented instructions on original K6-2.[3][4] |
| PI2FW mm1, mm2/m64 | 0F 0F /r 0C | Packed 16-bit Integer to Floating-point Conversion | |
| PSWAPD mm1, mm2/m64 | 0F 0F /r BB | Packed Swap Doubleword | Uses same opcode as older undocumented K6-2 PSWAPW instruction.[4] |
| PFNACC mm1, mm2/m64 | 0F 0F /r 8A | Packed Floating-Point Negative Accumulate | |
| PFPNACC mm1, mm2/m64 | 0F 0F /r 8E | Packed Floating-Point Positive-Negative Accumulate | For complex number arithmetic. |
3dnow! instructions specific to Geode GX and LX[edit]
| Instruction | Opcode | Meaning |
|---|---|---|
| PFRCPV mm1, mm2/m64 | 0F 0F /r 86 | Packed Floating-point Reciprocal Approximation |
| PFRQSRTV mm1, mm2/m64 | 0F 0F /r 87 | Packed Floating-point Reciprocal Square Root Approximation |
SSE5 derived instructions[edit]
SSE5 was a proposed SSE extension by AMD. The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor. AMD chose not to implement SSE5 as originally proposed, however, derived SSE extensions were introduced.
XOP[edit]
Introduced with the bulldozer processor core, removed again from Zen (microarchitecture) onward.
A revision of most of the SSE5 instruction set
FMA4[edit]
Supported in AMD processors starting with the Bulldozer architecture, removed in Zen. Not supported by any intel chip as of 2017.
Fused multiply-add with four operands. FMA4 was realized in hardware before FMA3.
| Instruction | Opcode | Meaning | Notes |
|---|---|---|---|
| VFMADDPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 69 /r /is4 | Fused Multiply-Add of Packed Double-Precision Floating-Point Values | |
| VFMADDPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 68 /r /is4 | Fused Multiply-Add of Packed Single-Precision Floating-Point Values | |
| VFMADDSD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6B /r /is4 | Fused Multiply-Add of Scalar Double-Precision Floating-Point Values | |
| VFMADDSS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6A /r /is4 | Fused Multiply-Add of Scalar Single-Precision Floating-Point Values | |
| VFMADDSUBPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 5D /r /is4 | Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values | |
| VFMADDSUBPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 5C /r /is4 | Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values | |
| VFMSUBADDPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 5F /r /is4 | Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values | |
| VFMSUBADDPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 5E /r /is4 | Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values | |
| VFMSUBPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6D /r /is4 | Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values | |
| VFMSUBPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6C /r /is4 | Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values | |
| VFMSUBSD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6F /r /is4 | Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values | |
| VFMSUBSS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 6E /r /is4 | Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values | |
| VFNMADDPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 79 /r /is4 | Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values | |
| VFNMADDPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 78 /r /is4 | Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values | |
| VFNMADDSD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7B /r /is4 | Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values | |
| VFNMADDSS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7A /r /is4 | Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values | |
| VFNMSUBPD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7D /r /is4 | Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values | |
| VFNMSUBPS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7C /r /is4 | Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values | |
| VFNMSUBSD xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7F /r /is4 | Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values | |
| VFNMSUBSS xmm0, xmm1, xmm2, xmm3 | C4E3 WvvvvL01 7E /r /is4 | Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values |
AMD Trailing Bit Manipulation Instructions[edit]
AMD introduced TBM together with BMI1 in its Piledriver[5] line of processors; later AMD Jaguar and Zen-based processors do not support TBM.[6] No Intel processors (as of 2020) support TBM.
| Instruction | Description[7] | Equivalent C expression[8] |
|---|---|---|
| BEXTR | Bit field extract (with immediate) | (src >> start) & ((1 << len) - 1)
|
| BLCFILL | Fill from lowest clear bit | x & (x + 1)
|
| BLCI | Isolate lowest clear bit | ~(x + 1) |
| BLCIC | Isolate lowest clear bit and complement | ~x & (x + 1)
|
| BLCMSK | Mask from lowest clear bit | x ^ (x + 1)
|
| BLCS | Set lowest clear bit | (x + 1) |
| BLSFILL | Fill from lowest set bit | (x - 1) |
| BLSIC | Isolate lowest set bit and complement | (x - 1) |
| T1MSKC | Inverse mask from trailing ones | (x + 1) |
| TZMSK | Mask from trailing zeros | ~x & (x - 1)
|
Instructions from other vendors[edit]
Instructions specific to NEC V-series processors[edit]
These instructions are specific to the NEC V20/V30 CPUs and their successors, and do not appear in any non-NEC CPUs. Many of their opcodes have been reassigned to other instructions in later non-NEC CPUs.
| Opcode | Instruction | Description | Available on |
|---|---|---|---|
| 0F 10 /0 | TEST1 r/m8, CL | Test one bit.
First argument specifies an 8/16-bit register or memory location. Second argument specifies which bit to test. |
All V-series[9] except V30MZ[10] |
| 0F 11 /0 | TEST1 r/m16, CL | ||
| 0F 18 /0 ib | TEST1 r/m8, imm8 | ||
| 0F 19 /0 ib | TEST1 r/m16, imm8 | ||
| 0F 12 /0 | CLR1 r/m8, CL | Clear one bit. | |
| 0F 13 /0 | CLR1 r/m16, CL | ||
| 0F 1A /0 ib | CLR1 r/m8, imm8 | ||
| 0F 1B /0 ib | CLR1 r/m16, imm8 | ||
| 0F 14 /0 | SET1 r/m8, CL | Set one bit. | |
| 0F 15 /0 | SET1 r/m16, CL | ||
| 0F 1C /0 ib | SET1 r/m8, imm8 | ||
| 0F 1D /0 ib | SET1 r/m16, imm8 | ||
| 0F 16 /0 | NOT1 r/m8, CL | Invert one bit. | |
| 0F 17 /0 | NOT1 r/m16, CL | ||
| 0F 1E /0 ib | NOT1 r/m8, imm8 | ||
| 0F 1F /0 ib | NOT1 r/m16, imm8 | ||
| 0F 20 | ADD4S | Add Nibble Strings.
Performs a string addition of integers in packed BCD format (2 BCD digits per byte). DS:SI points to a source integer, ES:DI to a destination integer, and CL provides the number of digits to add. The operation is then: destination <- destination + source | |
| 0F 22 | SUB4S | Subtract Nibble Strings.
destination <- destination - source | |
| 0F 26 | CMP4S | Compare Nibble Strings. | |
| 0F 28 /0 | ROL4 r/m8 | Rotate Left Nibble.
Concatenates its 8-bit argument with the bottom 4 bits of AL to form a 12-bit bitvector, then left-rotates this bitvector by 4 bits, then writes this bitvector back to its argument and the bottom 4 bits of AL. | |
| 0F 2A /0 | ROR4 r/m8 | Rotate Right Nibble. Similar to ROL4, except performs a right-rotate by 4 bits. | |
| 0F 30 /r | EXT r8,r8 | Bitfield extract.
Perform a bitfield read from memory. DS:SI (DS0:IX in NEC nomenclature) points to memory location to read from, first argument specifies bit-offset to read from, and second argument specifies the number of bits to read minus 1. The result is placed in AX. After the bitfield read, SI and the first argument are updated to point just beyond the just-read bitfield. | |
| 0F 38 /0 ib | EXT r8,imm8 | ||
| 0F 31 /r | INS r8,r8 | Bitfield Insert.
Perform a bitfield write to memory. ES:DI (DS1:IY in NEC nomenclature) points to memory location to write to, AX contains data to write, first argument specifies bit-offset to write to, and second argument specifies the number of bits to write minus 1. After the bitfield write, DI and the first argument are updated to point just beyond the just-written bitfield. | |
| 0F 39 /0 ib | INS r8,imm8 | ||
| 64 | REPC | Repeat if carry. Instruction prefix for use with CMPS/SCAS. | |
| 65 | REPNC | Repeat if not carry. Instruction prefix for use with CMPS/SCAS. | |
| 66 /r
67 /r |
FPO2 | "Floating Point Operation 2": extra escape opcodes for floating-point coprocessor, in addition to the standard D8-DF ones used for x87.
Used by the NEC 72291 floating-point coprocessor. A listing of the opcodes/instructions supported by the 72291 is available.[11] | |
| 0F FF ib | BRKEM imm8 | Break to 8080 emulation mode.
Jump to an address picked from the Interrupt Vector Table using the imm8 argument, similar to the INT instruction, but start executing as Intel 8080 code rather than x86 code. |
V20, V30, V40, V50[9] |
| 0F E0 ib | BRKXA imm8 | Break to Extended Address Mode.
Jump to an address picked from the Interrupt Vector Table using the imm8 argument. Enables a simple memory paging mechanism after reading the IVT but before executing the jump. The paging mechanism uses an on-chip page table with 16Kbyte pages and no access rights checking.[12] |
V33, V53[9] |
| 0F F0 ib | RETXA imm8 | Return from Extended Address Mode.
Jump to an address picked from the Interrupt Vector Table using the imm8 argument. Disables paging after reading the IVT but before executing the jump. | |
| 0F 25 | MOVSPA | Transfer both SS and SP of old register bank after the bank has been switched by an interrupt or BRKCS instruction. | V25, V35,[13] V55[14] |
| 0F 2D /0 | BRKCS r16 | Perform software interrupt with context switch to register bank specified by low 3 bits of r16. | |
| 0F 91 | RETRBI | Return from register bank context switch interrupt. | |
| 0F 92 | FINT | Finish Interrupt. | |
| 0F 94 /7 | TSKSW r16 | Perform task switch to register bank indicated by low 3 bits of r16. | |
| 0F 95 /7 | MOVSPB r16 | Transfer SS and SP of current register bank to register bank indicated by low 3 bits of r16. | |
| 0F 9C ib ib rel8 | BTCLR imm8,imm8,cb | Bit Test and Clear.
The first argument specifies a V25/V35 Special Function Register to test a bit in. The second argument specifies a bit position in that register. The third argument specifies a short branch offset. If the bit was set to 1, then it is cleared and a short branch is taken, else the branch is not taken. | |
| 0F 9E | STOP | CPU Halt. Differs from conventional 8086 HLT in that the clock is stopped too, so that an NMI or CPU reset is needed to resume operation. | |
| F1 ib | BRKS imm8 | Break and Enable Software Guard.
Jump to an address picked from the Interrupt Vector Table using the imm8 argument, and then continue execution with "Software Guard" enabled. The "Software Guard" is an 8-bit Substitution cipher that, during instruction fetch/decode, translates opcode bytes using a 256-entry lookup table stored in an on-chip Mask ROM. |
V25, V35 "Software Guard"[15] |
| 63 ib | BRKN imm8 | Break and Enable Native Mode. Similar to BRKS, excepts disables "Software Guard" rather than enabling it. | |
| 8C /6 | MOV r/m,DS3 | Move to/from DS2 and DS3 extended segment registers. These registers, specific to V55, act similar to regular x86 real-mode segment registers except that they are left-shifted by 8 rather than 4, enabling access to 16MB of memory. | V55[14] |
| 8C /7 | MOV r/m,DS2 | ||
| 8E /6 | MOV DS3,r/m | ||
| 8E /7 | MOV DS2,r/m | ||
| 0F 76[16] | PUSH DS3 | ||
| 0F 77 | POP DS3 | ||
| 0F 7E | PUSH DS2 | ||
| 0F 7F | POP DS2 | ||
| 0F 36 /r | MOV DS3,r16,m32 | Instructions to load both extended segment register and general-purpose register at once, similar to 8086's LDS and LES instructions | |
| 0F 3E /r | MOV DS2,r16,m32 | ||
| 63 | DS2: | Segment prefixes for the DS2 and DS3 extended segments | |
| D6 | DS3: | ||
| F1 | IRAM: | Register File Override Prefix. Will cause memory operands to index into register file rather than general memory | |
| 0F 3C /0 | BSCH r/m8 | Count Trailing Zeroes and store result in CL. Sets ZF=1 for all-0s input. | |
| 0F 3D /0 | BSCH r/m16 | ||
| 0F 96 ib ib | RSTWDT imm8,imm8 | Watchdog Timer Manipulation Instruction | |
| 0F 9D ib ib rel8 | BTCLRL imm8,imm8,cb | Bit test and clear for second bank of special purpose registers (similar to BTCLR) | |
| 0F E0 iw | QHOUT imm16 | Queue manipulation instructions | |
| 0F E1 iw | QOUT imm16 | ||
| 0F E2 iw | QTIN imm16 | ||
| 0F 9F | IDLE | Put CPU in idle mode | V55SC[17] |
| 0F 9A | ALBIT | Dedicated fax instructions | V55PI[14] |
| 0F 9B | COLTRP | ||
| 0F 93 | MHENC | ||
| 0F 97 | MRENC | ||
| 0F 78 | SCHEOL | ||
| 0F 79 | GETBIT | ||
| 0F 7C | MHDEC | ||
| 0F 7D | MRDEC | ||
| 0F 7A | CNVTRP | ||
| 63 | (no mnemonic) | Designated opcode for termination of the x86 emulation mode on the NEC V60.[18] | V60, V70 |
Instructions specific to Cyrix and Geode CPUs[edit]
These instructions are present in Cyrix CPUs as well as NatSemi/AMD Geode CPUs derived from Cyrix microarchitectures (Geode GX and LX, but not NX). They are also present in Cyrix manufacturing partner CPUs from IBM, ST and TI, as well as a few SoCs such as STPC ATLAS and ZFMicro ZFx86.[19] Many of these opcodes have been reassigned to other instructions in later non-Cyrix CPUs.
| Opcode | Instruction | Description | Available on |
|---|---|---|---|
| 0F 78 /r | SVDC m80,sreg | Save segment register and descriptor to memory as a 10-byte data structure.
The first 8 bytes are the descriptor, the last two bytes are the selector.[20] |
System Management Mode instructions.
Not present on stepping A of Cx486SLC and Cx486DLC.[21] Present on Cx486SLC/e[22] and all later Cyrix CPUs. Present on all Cyrix-derived Geode CPUs. |
| 0F 79 /r | RSDC sreg,m80 | Restore segment register and descriptor from memory | |
| 0F 7A /0 | SVLDT m80 | Save LDTR and descriptor | |
| 0F 7B /0 | RSLDT m80 | Restore LDTR and descriptor | |
| 0F 7C /0 | SVTS m80 | Save TSR and descriptor | |
| 0F 7D /0 | RSTS m80 | Restore TSR and descriptor | |
| 0F 7E | SMINT | System management software interrupt.
Uses 0F 7E encoding on Cyrix 486, 5x86, 6x86 and ZFx86. Uses 0F 38 encoding on Cyrix 6x86MX, MII, MediaGX and Geode. | |
| 0F 38 | |||
| 0F 36 /0 | RDSHR r/m32 | Read SMM Header Pointer Register | Cyrix 6x86MX[23] and MII |
| 0F 37 /0 | WRSHR r/m32 | Write SMM Header Pointer Register | |
| 0F 3A | BB0_RESET | Reset BLT Buffer Pointer 0 to base | Cyrix MediaGX and MediaGXm[24]
NatSemi Geode GXm, GXLV, GX1 |
| 0F 3B | BB1_RESET | Reset BLT Buffer Pointer 1 to base | |
| 0F 3C | CPU_WRITE | Write to CPU internal special register (EBX=register-index, EAX=data) | |
| 0F 3D | CPU_READ | Read from CPU internal special register (EBX=register-index, EAX=data) | |
| 0F 39 | DMINT | Debug Management Mode Interrupt | NatSemi Geode GX2
AMD Geode GX, LX[25] |
| 0F 3A | RDM | Return from Debug Management Mode |
Cyrix EMMI instructions[edit]
Added with 6x86MX from Cyrix, deprecated now
PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW
Instructions specific to Chips and Technologies CPUs[edit]
The C&T F8680 PC/Chip is a system-on-a-chip featuring an 80186-compatible CPU core, with a few additional instructions to support the F8680-specific "SuperState R"[26] supervisor/system-management feature. Some of the added instructions for "SuperState R" are:[27]
| Opcode | Instruction | Description |
|---|---|---|
| FE F8 | LFEAT AX | Load datum into F8680 "CREG" configuration register (AH=register-index, AL=datum)[28] |
| FE F0 ib | STFEAT AL,imm8 | Read F8680 status register into AL (imm8=register-index) |
C&T also developed a 386-compatible processor known as the Super386. This processor supports, in addition to the basic Intel 386 instruction set, a number of instructions to support the Super386-specific "SuperState V" system-management feature. The added instructions for "SuperState V" are:[29]
| Opcode | Instruction | Description |
|---|---|---|
| 0F 18 /0 | SCALL r/m | Call SMM interrupt handler[30][31] |
| 0F 19 | SRET | Return from SMM interrupt handler |
| 0F 1A | SRESUME | Return from SMM with interrupts disabled for one instruction |
| 0F 1B | SVECTOR | Exit from SMM and issue a shutdown cycle |
| 0F 1E | EPIC | Load one of the six interrupt or I/O traps |
| 0F 3C | RARF1 | Read from bank 1 of the register file (includes visible and invisible CPU registers) |
| 0F 3D | RARF2 | Read from bank 2 of the register file |
| 0F 3E | RARF3 | Read from bank 3 of the register file |
| 0F F0 | LTLB | Load TLB with page table entry |
| 0F F1 | RCT | Read cache tag |
| 0F F2 | WCT | Write cache tag |
| 0F F3 | RCD | Read cache data |
| 0F F4 | WCD | Write cache data |
| 0F F5 | RTLBPA | Read TLB data (physical address) |
| 0F F6 | RTLBLA | Read TLB tag (linear address) |
| 0F F7 | LCFG | Load configuration register |
| 0F F8 | SCFG | Store configuration register |
| 0F F9 | RGPR | Read general-purpose register or any bank of register file |
| 0F FA | RARF0 | Read from bank 0 of the register file |
| 0F FB | RARFE | Read from extra bank of the register file |
| 0F FD | WGPR | Write general-purpose register or any bank of register file |
| 0F FE | WARFE | Write extra bank of the register file |
Instructions specific to ALi/DM&P M6117 MCUs[edit]
The M6117 series of embedded microcontrollers feature a 386SX-class CPU core with a few M6117-specific additions to the Intel 386 instruction set. The ones documented for DM&P M1167D are:[32]
| Opcode | Instruction | Description |
|---|---|---|
| F1 | BRKPM | System management interrupt - enters "hyper state mode" |
| D6 E6 | RETPM | Return from "hyper state mode" |
| D6 CA 03 A0 | LDUSR UGRS,EAX | Set page address of SMI entry point |
| D6 C8 03 A0 | (mnemonic not listed) | Read page address of SMI entry point |
| D6 FA 03 02 | MOV PWRCR,EAX | Write to power control register |
Instructions present in specific 80387 clones[edit]
Several 80387-class coprocessors provided extra instructions in addition to the standard 80387 ones, none of which are present in later processors:
| Instruction | Opcode | Description | Available on |
|---|---|---|---|
| FRSTPM | DB F4[33]
or DB E5[34] |
FPU Reset Protected Mode.
Instruction to signal to the FPU that the main CPU is exiting protected mode, similar to how the FSETPM instruction is used to signal to the FPU that the CPU is entering protected mode. Different sources provide different encodings for this instruction. |
Intel 287XL |
| FNSTDW AX | DF E1 | Store FPU Device Word to AX | Intel 387SL[34][35] |
| FNSTSG AX | DF E2 | Store FPU Signature Register to AX | |
| FSBP0 | DB E8 | Select Coprocessor Register Bank 0 | IIT 2c87, 3c87[34][36] |
| FSBP1 | DB EB | Select Coprocessor Register Bank 1 | |
| FSBP2 | DB EA | Select Coprocessor Register Bank 2 | |
| FSBP3 | DB E9[37] | Select Coprocessor Register Bank 3 (undocumented) | |
| F4X4,
FMUL4X4 |
DB F1 | Multiply 4-component vector with 4x4 matrix. For proper operation, the matrix must be preloaded into Coprocessor Register banks 1 and 2 (unique to IIT FPUs), and the vector must be loaded into Coprocessor Register Bank 0. Example code is available.[36][38] | |
| FTSTP | D9 E6 | Equivalent to FTST followed by a stack pop. | Cyrix 387+[38] |
| FRINT2 | DB FC | Round st(0) to integer, with round-to-nearest rounding. | Cyrix EMC87, 83s87, 83d87, 387+[38][34] |
| FRICHOP | DD FC | Round st(0) to integer, with round-to-zero rounding. | |
| FRINEAR | DF FC | Round st(0) to integer, with round-to-nearest ties-away-from-zero rounding. |
See also[edit]
References[edit]
- ↑ Intel Itanium Architecture Software Developer's Manual, volume 4, (document number: 323208, revision 2.3, may 2010).
- ↑ "Windows 10 64-bit requirements: Does my CPU support CMPXCHG16b, PrefetchW and LAHF/SAHF?".
- ↑ Grzegorz Mazur, AMD 3DNow! undocumented instructions
- ↑ 4.0 4.1 "Archived copy". grafi.ii.pw.edu.pl. Archived from the original on 30 January 2003. Retrieved 22 February 2022. Unknown parameter
|url-status=ignored (help)CS1 maint: Archived copy as title (link) - ↑ Hollingsworth, Brent. "New "Bulldozer" and "Piledriver" instructions" (PDF). Advanced Micro Devices, Inc. Retrieved 11 December 2014.
- ↑ "Family 16h AMD A-Series Data Sheet" (PDF). amd.com. AMD. October 2013. Retrieved 2014-01-02.
- ↑ "AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions" (PDF). amd.com. AMD. October 2013. Retrieved 2014-01-02.
- ↑ "tbmintrin.h from GCC 4.8". Retrieved 2014-03-17.
- ↑ 9.0 9.1 9.2 NEC 16-bit V-series User's Manual
- ↑ NEC V30MZ Preliminary User's Manual, p.14
- ↑ NEC 72291 FPU: an instruction listing can be found in the HP 64873 V-series Cross Assembler Reference, pages F-31 to F-34.
- ↑ NEC 16-bit V-series Microprocessor Data Book, 1991, p. 360-361
- ↑ Renesas Data Sheet MOS Integrated Circuit uPD70320
- ↑ 14.0 14.1 14.2 NEC V55PI 16-bit microprocessor Data Sheet, U11775E
- ↑ NEC 16-bit V-series Microprocessor Data Book, 1991, p. 765-766
- ↑ NEC V55PI Users Manual Instruction, U10231J (Japanese). Opcodes for PUSH/POP DS2/DS3 listed in macro definitions on p. 378.
- ↑ NEC V55SC 16-bit Microprocessor Preliminary Data Sheet (O.D.No ID-8206A, March 1993), p.127. Located on Apr 20, 2022 by searching for "nec v55sc" at datasheetarchive.com.
- ↑ NEC uPD70616 Programmer's Reference Manual (november 1986), p.287
- ↑ ZFMicro, ZFx86 System-on-a-chip Data Book 1.0 Rev D, june 5, 2005, section 2.2.6.3, page 76
- ↑ Texas Instruments, TI486 Microprocessor Reference Guide, 1993, section A.14, page 308
- ↑ Debbie Wiles, CPU identification, archived on 2004-06-04
- ↑ Cyrix 486SLC/e Data Sheet (1992), section 2.6.4
- ↑ Cyrix 6x86MX Data Book, section 2.15.3
- ↑ Cyrix MediaGX Data Book, section 4.1.5
- ↑ AMD Geode LX Processors Data Book, section 8.3.4
- ↑ BYTE Magazine, november 1991, page 245
- ↑ Institute Of Oceanographic Sciences, Sonic buoy - Formatter Handbook contains some F8680 instruction macros on page 34
- ↑ The F8680 PC/Chip System Design Guide contains descriptions of many of the F8680 CREG registers.
- ↑ Microprocessor Report, System Management Mode Explained (vol 6, no. 8, june 17, 1992) - includes a list of the C&T Super386 "SuperState V" opcodes.
- ↑ Michal Necasek, More on the C&T Super386
- ↑ Corexor, Calling C&T SCALL safely
- ↑ DM&P, M6117D : System on a chip, pages 31,34,68. Archived on Jul 20,2006.
- ↑ Intel "Intel287 XL/XLT Math Coprocessor", (oct 1992, order no 290376-003) p.33
- ↑ 34.0 34.1 34.2 34.3 Potemkin's Hacker Group's OPCODE.LST, v4.51
- ↑ Intel "Intel387 SL Mobile Math Coprocessor" (feb 1992, order no 290427-001), appendix A. Located on Jan 7, 2022 by searching for "intel387 sl" at datasheetarchive.com.
- ↑ 36.0 36.1 IIT 3c87 Advanced Math CoProcessor Data Book
- ↑ Harald Feldmann, Hamarsoft 86BUGS List
- ↑ 38.0 38.1 38.2 Norbert Juffa "Everything You Always Wanted To Know About Math Coprocessors", 01-oct-94 revision
This article "List of discontinued x86 instructions" is from Wikipedia. The list of its authors can be seen in its historical and/or the page Edithistory:List of discontinued x86 instructions. Articles copied from Draft Namespace on Wikipedia could be seen on the Draft Namespace of Wikipedia and not main one.
|
This page exists already on Wikipedia. |
