MRISC32
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| File:MRISC32-logo.svg | |
| Bits | 32 |
|---|---|
| Introduced | 2018 |
| Design | RISC |
| Type | Load-store |
| Encoding | Fixed (32 bits) |
| Branching | Compare-and-branch |
| Endianness | Little-endian |
| Extensions |
|
| Open | Yes, royalty free |
| Registers | |
| General purpose | 32 (Shared integer and floating-point) |
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MRISC32 is an open and royalty free RISC/vector instruction set architecture.[1]
Instruction set[edit]
The instruction set is a load-store architecture, with fixed width instruction encoding (32 bits per instruction word) and provisions for operating on both scalar and vector operands with most instructions.[2]
Registers[edit]
MRISC32 provides 32 general purpose scalar registers, each 32 bits in size, that can hold any type of data: integer values, addresses, floating-point values and packed integer or floating-point values (SIMD in the form of two 16-bit values or four 8-bit values).
When the Vector operation module (VM) is implemented, 32 vector registers are also provided. Each vector register is organized as a collection of 32-bit elements. The number of elements of a vector register is implementation defined, and mechanisms are provided that allow software to be binary compatible across implementations with different vector register sizes. Like the scalar registers, vector elements can hold integer values, addresses, floating-point values and packed data types.
Example code[edit]
The assembly language program below demonstrates how functions are called in the standard MRISC32 calling convention. When a function is called, the return address is stored in the link register (LR). The value of this register needs to be preserved by a function if the function itself calls other functions (as in the example). The standard method for preserving registers is to store them on the stack (pointed to by the stack pointer register, SP).
The example uses a large memory model with PC-relative addressing, which means that two instructions are needed for forming far addresses (with a range of PC ± 2GB). It is also possible to use a small memory model whereby only a single instruction is needed (with a range of PC ± 4MB). A linker that implements linker relaxation will automatically use the shorter form when possible.
5bbd3ffc 2fdd0000 d4200006 582101c0 d7c00000 c7c00056 0fdd0000 5bbd0004 d8200000 c3c00000 |
.text
.global main
main:
; Preserve LR on the stack
add sp, sp, #-4
stw lr, [sp, #0]
; Call puts(hello)
ldi r1, #hello@pc
call #puts@pc
; Restore LR from the stack
ldw lr, [sp, #0]
add sp, sp, #4
; Return with the value zero
ldi r1, #0
ret
.section .rodata
hello:
.string "Hello world!"
|
Implementations[edit]
The first implementation of MRISC32 is a soft microprocessor called MRISC32-A1.[3] The CPU is a pipelined design capable of executing one instruction per clock cycle. The design is implemented in VHDL and intended for running in FPGAs.
References[edit]
- ↑ "The MRISC32 - A vector first CPU design". 5 December 2022.
- ↑ "MRISC32 Instruction Set Manual" (PDF). 5 December 2022.
- ↑ "MRISC32-A1 - A VHDL implementation of the MRISC32 ISA". 8 December 2022.
External links[edit]
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