Mill Computing
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Formerly | Out-of-the-Box Computing |
|---|---|
| ISIN | 🆔 |
| Founded 📆 | 2004 |
| Founder 👔 | |
Area served 🗺️ | |
Key people |
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| Members | |
Number of employees | |
| 🌐 Website | millcomputing |
| 📇 Address | |
| 📞 telephone | |
Mill Computing, Inc. is a company developing a new general-purpose computer architecture known as the Mill, currently running in simulation with an FPGA-prototype in progress. The Mill architecture has been presented as a series of recorded lectures held at universities and companies in order to get feedback from the industry and to seek funding. As of 2018, Mill Computing holds 14 patents for various techniques used in the architecture, with more patents pending.[1][2][3]
The Mill architecture[edit]
The Mill differs from conventional architectures such as the x86 in multiple ways. Most notably, it is statically scheduled with each instruction taking a known fixed amount of cycles. This allows the compiler to optimize the order of execution and resulting ILP, unlike on an out-of-order machine where this is done by the CPU at runtime. Being wide-issue, it is capable of executing 30+ MIMD instructions per cycle. The Mill was inspired by the efficiency of DSPs but can also run general purpose code with branches like a typical CPU. With this design, the company expects the architecture to achieve the same performance as an x86 at 10% of the power usage.[4]
Instead of general purpose registers, the Mill makes use of a structure called the belt. Conceptually, it can be thought of as a fixed size queue or shift register. Instructions refer to input values on the belt by temporal indexing, and output values are implicitly placed in the front of the belt, pushing older values off the belt and storing them in reserved memory only if later needed. As all basic instructions take a fixed amount of cycles, the compiler knows where on the belt each value will be each cycle. Special handling is done for memory load instructions where it is not known how fast the data will arrive on the belt, possibly inducing a stall.
The Mill makes extensive use of metadata associated with values on the belt. Values can for instance be tagged as being invalid, avoiding hazards and allowing aggressive branch prediction without affecting global state. It also enables vectorization of while-loops, pipelining each iteration. A pointer on a Mill is 64 bits, with 4 bits reserved for metadata. Uninitialized memory is implicitly zero, avoiding unnecessary memory access and improving security.[5]
See also[edit]
References[edit]
- ↑ "Mill Computing, Inc".
- ↑ "Startup Seeks Funds to Realize 'Belt' Processor". Electronics360. 2013-12-16.
- ↑ "Mill Computing heads to FPGA demo, seeks funds". eeNews Europe. 2017-01-12.
- ↑ "Interview: New Mill CPU Architecture Explanation For Humans". Hackaday. 2013-11-18.
- ↑ "Mill Computing docs".
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