Dr. Naveed Sherwani
| Dr. Naveed Sherwani | |
|---|---|
| File:Naveed Sherwani.jpgNaveed Sherwani.jpg | |
| Born | April 24, 1960 Karachi, Sindh, Pakistan |
| 🏳️ Nationality | American Pakistani |
| 🏫 Education | NED University of Engineering & Technology, University of Nebraska–Lincoln |
| 💼 Occupation | * Founder/Co-Founder
|
Dr. Naveed Sherwani is a Pakistani—American entrepreneur, semiconductor industry veteran, and academician. He has founded or co-founded 17 companies, raising over $1 billion in funding, and creating more than $5 billion in value across various ventures.[citation needed]
Early life and education
Born in Karachi, Pakistan in 1960, Sherwani graduated with a Bachelor of Science in Electrical Engineering from NED University of Engineering and Technology in 1983. He then pursued graduate studies in the United States, earning a Master of Science and a Ph.D. in Computer Engineering from the University of Nebraska–Lincoln. During his doctoral studies, he served as a teaching assistant.
Academic career
From 1988 to 1994, Sherwani was a professor at Western Michigan University in Kalamazoo, Michigan. His research focused on areas such as ASICs, Computer-Aided Design (CAD) Algorithms, Very Large Scale Integration (VLSI), Electronic Design Automation (EDA), Combinatorics, Graph Theory, and Parallel Computing. He authored over 100 publications and books, including the textbook Algorithms for VLSI Physical Design Automation.[1]
Industry career
Sherwani joined Intel in 1994, where he contributed in designing and deploying Athena, a comprehensive chip development platform that enhanced the automation of microprocessor projects across the company. His contributions earned him the Intel Achievement Award in 1997.
In 2003, Sherwani co-founded Open-Silicon, a company that helped transform the ASIC industry by reducing the cost and complexity of chip development. The company was a fabless semiconductor company that focused on custom System on Chip (SoC) designs. In December 2007, Unicorn Investment Bank acquired a 75% stake in Open-Silicon for $190 million, while the remaining 25% remained employee-owned.[2][3][4][5] Open-Silicon was acquired by SiFive in September 2021 and was renamed as OpenFive. The unit was subsequently sold by SiFive in March 2022 to Alphawave Semi.[6]
Sherwani founded PeerNova in 2013, a company focused on blockchain-based financial services. He served as Chairman, President, and CEO, until leaving in 2016.
As Chairman, President, and CEO of SiFive (serving from 2017 to 2020), Sherwani was instrumental in the company's growth from a 20-person startup to a global enterprise valued at $2 billion. He also co-founded a federation of RISC-V companies, including StarFive, LeapFive, SemiFive, and ChinaFive, to promote the open-source RISC-V architecture.[7][8]
In 2021, Sherwani founded Rapid Silicon, a company focused on developing AI-enabled application-specific FPGAs. As Chairman and CEO, he led the company to raise over $45 million in seed and Series A funding. Under his leadership, Rapid Silicon introduced the first open-source AI-enabled EDA platform for FPGAs, aimed at accelerating design cycles and enhancing efficiency in edge and IoT applications.[9][10][11]
In 2024, Sherwani was appointed CEO of the National Semiconductor Hub (NSH) in Saudi Arabia, a strategic initiative aimed at establishing the Kingdom as a global center for semiconductor design. Under his leadership, the NSH has set ambitious goals to attract 50 fabless semiconductor companies by 2030, supported by a $266 million investment fund. The hub provides a ecosystem for startups, including incentives, training programs, and access to capital. By July 2025, the NSH aims to achieve its first chip tapeout from Saudi Arabia.[12][13][14]
Sherwani is also a non-executive director at MosChip Technologies and serves on the boards of several other companies. Additionally, he has been involved in various advisory roles and strategic initiatives within the semiconductor industry.
Books and academic publications
Dr. Naveed Sherwani is a prolific author with over 100 publications spanning peer-reviewed journal articles, conference papers, and academic textbooks in the fields of VLSI Design, Computer-Aided Design (CAD), Parallel Computing, and Graph Theory. His work has been widely cited and continues to influence the semiconductor industry and academic research alike.
- Algorithms for VLSI Physical Design Automation (First published in 1993; multiple editions)[15]
- This textbook is considered a foundational reference in VLSI design and is widely adopted in graduate-level engineering curricula across the globe. It covers core topics such as placement, routing, floorplanning, and optimization techniques in physical design automation.
- A Provably Good Multilayer Topological Planar Routing Algorithm in IC Layout Designs, IEEE, Published 1993, DOI:10.1109/43.184844
- Algorithms for VLSI Physical Automation Second Edition, Springer, Published 1995, ISBN 978-1-4613-5997-5
- Routing in the Third Dimension: From VLSI Chips to MCMs, Wiley-IEEE, Published 1995, ISBN 0-7803-1089-6
- Introduction to Multichip Modules, Wiley-Interscience, Published 2009, ISBN 978-0471114383
- Computer Aided Design and Design Automation (Physical Design Automation Chapter), CRC Press, Published 2009, ISBN 9781315219103
- Computing in the 90's, Springer, Published 1991, ISBN 978-0387976280
- Efficient Edge Domination Problems in Graphs, Published 1993, DOI: 10.1016/0020-0190(93)90084-M
- Integrated Floorplanning and Interconnect Planning, Springer, Published 2001, DOI:10.1007/978-1-4757-3415-7_1
- Incomplete hypercubes: Algorithms and Embeddings, The Journal of Supercomputing, Published 1994, DOI:10.1007/BF01204731
- EDA Challenges Facing Future Microprocessor Design, IEEE, Published 2000, DOI:10.1109/43.898828
- Effective Buffer Insertion of Clock Tree for High-Speed VLSI Circuits, Published 1992, DOI:10.1016/0026-2692(92)90026-W
- New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals, IEEE, Published 1991, DOI:10.1145/127601.127642
- Distance in Stratified Graphs, Springer, Published 2000, DOI: 10.1023/A:1022428917827
- Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs, Published 2002, DOI:10.1145/505388.505403
- Over-the-Cell Routers for New Cell Model, IEEE, Published 1992, DOI:10.1109/DAC.1992.227814
- Algorithms for Three-Layer Over-the-Cell Channel Routing, IEEE, Published 1991, DOI:10.1109/ICCAD.1991.185295
- Over-the-Cell Channel Routing for High Performance Circuits, IEEE, Published 1992, DOI:10.1109/DAC.1992.227815
- A Graph Theoretic Approach to Single Row Routing Problems, IEEE, Published 1988, DOI:10.1109/ISCAS.1988.15199
- On Optimal Embeddings into Incomplete Hypercubes, IEEE, Published 1991, DOI:10.1109/IPPS.1991.153813
- Utilization of Vacant Terminals for Improved Over-the-Cell Channel Routing, IEEE, Published 1993, DOI:10.1109/43.229752
- A Lower Bound on Embedding Large Hypercubes into Small Hypercubes, Purdue University, Published 1990
- New Channel Segmentation Model and Associated Routing Algorithm for High Performance FPGAs, IEEE, Published 1992, DOI:10.1109/ICCAD.1992.279404
- On the Use of Flexible, Rectilinear Blocks to Obtain Minimum-Area Floorplans in Mixed Block and Cell Designs, ACM, Published 2000, DOI:10.1145/329458.329470
- Floorplanning for Mixed Macro Block and Standard Cell Designs, IEEE, Published 1994, DOI:10.1109/GLSV.1994.290001
- SRC Physical Design Top Ten Problems, Published 1999, 299996.300022
- Algorithmic Aspects of Three Dimensional MCM Routing, IEEE, Published 1994, DOI:10.1109/DAC.1994.204133
- Clock Layout for High-Performance ASIC Based on Weighted Center Algorithm, IEEE, Published 1991, DOI:10.1109/ASIC.1991.242886
- Programmable Multichip Modules, IEEE, Published 1993, DOI:10.1109/40.207086
- Zero Skew Clock Routing in Multiple-Clock Synchronous Systems, IEEE, Published 1992, DOI:10.1109/ICCAD.1992.279327
- Over-the-Cell Routing Algorithms for Industrial Cell Models, IEEE, Published 1994, DOI:10.1109/ICVD.1994.282673
- Physical Design Tradeoffs for ASIC Technologies, IEEE, Published 1993, DOI:10.1109/ASIC.1993.410811
- On Optimum Cell Models for Over-the-Cell Routing, Published 1993, DOI:10.1109/ICVD.1993.669647
- New Lower Bounds for Single Row Routing Problems, IEEE, Published 1989, DOI:10.1109/MWSCAS.1989.101909
- A New Heuristic for Single Row Routing Problems, IEEE, Published 1989, DOI:10.1145/74382.74411
- Zero Skew Clock Routing Algorithm for High Performance ASIC Systems, IEEE, Published 1993, DOI:10.1109/ASIC.1993.410812
- Middle Terminal Cell Models for Efficient Over-the-Cell Routing in High-Performance Circuits, IEEE, Published 1993, DOI:10.1109/92.250194
- MISER: An Integrated Three Layer Gridless Channel Router and Compacter, IEEE, Published 1990, DOI:10.1109/DAC.1990.114943
- Bus-Based Integrated Floorplanning, IEEE, Published 2002, DOI:10.1109/ISCAS.2002.1011493
- Single Row Routing with Bounded Number of Doglegs Per Net, IEEE, Published 1989, DOI:10.1109/ISCAS.1989.100288
- On Topological via Minimization and Routing, IEEE, Published 1991, DOI:10.1109/ICCAD.1991.185324
- A Unified Approach to Multilayer Over-the-Cell Routing, IEEE, Published 1994, DOI:10.1145/196244.196332
- Minimum Skew Multiple Clock Routing in Synchronous ASIC Systems, IEEE, Published 1992, DOI:10.1109/ASIC.1992.270315
- An Efficient Four Layer Over-the-Cell Router, IEEE, Published 1994, DOI:10.1109/ISCAS.1994.409228
- Optimal Algorithms for Restricted Single Row Routing Problems, IEEE, Published 1992, DOI:10.1109/MWSCAS.1991.252086
- CD3D: A Constraint-driven 3-dimensional Router for Thick Film Mcms, IEEE, Published 1994, DOI:10.1109/ICMCM.1994.753606
- Compact Hypercubes: Properties and Recognition, Springer, Published 1991, DOI:10.1007/3-540-54029-6_187
- Fully Normal Algorithms for Incomplete Hypercubes, IEEE, Published 1991, DOI:10.1109/IPPS.1991.153770
- A Parallel Algorithm for Single Row Routing Problems, Published 1992, DOI:10.1142/S0218126692000106
- High Performance Over-the-Cell Routing, IEEE, Published 1994, DOI:10.1109/ICVD.1994.282672
- Load Balancing Properties of Networks, IEEE, Published 1990, DOI:10.1109/MWSCAS.1990.140720
- DFM Rules!, ACM, Published 2005, DOI:10.1145/1065579.1065625
- A Minimum-Area Floorplanning Algorithm for MBC Designs, IEEE, Published 1996, DOI:10.1109/GLSV.1996.497593
- Layout Driven Synthesis or Synthesis Driven Layout?, IEEE, Published 1998, DOI:10.1109/ICVD.1998.646576
- Optimal Algorithms for Planar Over-the-Cell Routing Problems, IEEE, Published 1996, DOI:10.1109/43.543769
- A Parallel Single Row Routing Algorithm for Hypercube Multiprocessor, IEEE, Published 1992, DOI:10.1109/MWSCAS.1991.252195
- Optimal Algorithms for Planar Over-the-Cell Routing in the Presence of Obstacles, IEEE, Published 1995, DOI:10.1109/ICVD.1995.512068
- An Optimal Algorithm for Maximum Two Planar Subset Problem /spl lsqb/VLSI layout/spl rsqb/, IEEE, Published 1994, DOI:10.1109/GLSV.1994.289991
- COT - Customer Owned Trouble, Published 2003, DOI:10.1145/775832.775858
- Keynote Speech (K-4) ASICs in a Global Economy; The Industrialization of the Semiconductor Industry, IEEE, Published 2005, DOI: 10.1109/ICASIC.2005.1611382
- Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs, IEEE, Published 2009, DOI:10.1109/DFT.2009.63
Recognition and awards
As CEO of Open-Silicon and later SiFive, Sherwani personally led both companies to win the Global Semiconductor Alliance (GSA) Most Respected Private Semiconductor Company Award a combined total of five times.
In recognition of his contributions to the global semiconductor industry and his efforts to advance technological innovation, Sherwani was awarded the Sitara-e-Quaid-e-Azam in 2019 by the Government of Pakistan. This honor reflected his role in elevating Pakistan's presence in the international tech landscape. In 2025, he was further recognized with the Hilal-e-Imtiaz, one of the country’s most prestigious civilian awards, for his continued leadership in deep-tech entrepreneurship, semiconductor design, and talent development.[16] Beyond national accolades, Sherwani has been featured in numerous international industry publications and is a frequent speaker at major technology conferences, where he shares insights on chip design, innovation strategy, and the future of computing.[citation needed]
Personal life
Dr. Sherwani is s married to Sabahat Rafiq, and together they have one daughter.
References
- ↑ Sherwani, Naveed (1998). Algorithms for VLSI Physical Design Automation. New York: Springer. p. 602. ISBN 978-0792383932. Search this book on
- ↑ https://www.reuters.com/article/business/bahrain-s-unicorn-takes-over-u-s-microchip-firm-idUSL23633275/ Reuters. December 23, 2007
- ↑ https://www.meed.com/bahrains-unicorn-buys-into-us-technology-firm/ Meed Editorial. 23 December 2007
- ↑ "Open-Silicon".
- ↑ https://www.eetimes.com/bahrain-bank-buys-stake-in-open-silicon/ EE Times. December 24, 2007
- ↑ "Alphawave acquires SiFive's OpenFive business for $210 million". Data Center Dynamics. March 14, 2022.
- ↑ https://www.datacenterknowledge.com/servers/sifive-ceo-says-risc-v-servers-are-five-years-away- Data Center Knowledge. June 24, 2019
- ↑ https://www.eetimes.com/qualcomm-takes-stake-in-sifive/ EE Times. June 7, 2019
- ↑ "Podcast EP146: How Rapid Silicon Will Change Innovation with Naveed Sherwani".
- ↑ https://www.techinsights.com/blog/fpga-startup-rapid-silicon-enters-market?utm_source=direct&utm_medium=website Tech Insights
- ↑ https://www.businesswire.com/news/home/20230109005130/en/Rapid-Silicon-Announces-%2430M-Series-A-Round Business Wire Jan 9, 2023
- ↑ https://gulfnews.com/business/markets/saudi-arabia-launches-semiconductor-hub-with-sr1b-fund-1.1717671932177?utm.com Gulf News. June 06, 2024
- ↑ https://thebusinessfrontier.com/ksas-266m-tech-fund-to-lure-global-chipmakers/?utm.com Business Frontier. June 7, 2024
- ↑ https://saudigazette.com.sa/article/643394 Saudi Gazette. June 06, 2024
- ↑ Sherwani, Naveed (1998). Algorithms for VLSI Physical Design Automation. New York: Springer. p. 602. ISBN 978-0792383932. Search this book on
- ↑ https://dailythepatriot.com/pakistan-day-president-confers-highest-civil-awards-on-69-national-and-foreign-dignitaries/ The Patriot. March 23, 2025
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