Pep/7
The Pep/7 Computer Simulation (also known as Pep7) is a virtual machine that is used by professors of schools and colleges to explain and simplify the lowest level of computing (machine language). True to its name, Pep/7 has seven registers and four status bits.[1][2]
The Pep/7 is a direct descendant of the Pep/6 virtual machine,[3] the only major difference is that it has been expanded from 4KiB to 32KiB of system RAM. The machine code format remains the same.
Architecture[edit]
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Address Bus[edit]
The Pep/7 uses a 16-bit address bus, capable of addressing 65,536 bytes
Internal Registers[edit]
The CPU has two 16-bit general purpose registers, A and X, a base pointer register B, a stack pointer SP, and an instruction pointer PC. There is also a hidden register IR that is 8-bits wide and holds the currently executing opcode. It is not normally accessible by the programmer.
Instruction Set[edit]
The Pep/7's instruction set is simplistic, with only 32 possible opcodes. The instruction specifier consists of the opcode of 5 bits, a register selector (A or X) of 1 bit, and a memory access mode of 2 bits, with the opcode occupying the top 5 bits of a byte, the register selector in bit 2 and the address mode in bits 1 and 0.
| Mnemonic | Opcode | Flags Affected | Addressing modes available |
|---|---|---|---|
| STOP | 00000 | - | - |
| LOAD r | 00001 | NZ | idsx |
| STORE r | 00010 | - | dsx |
| ADD r | 00011 | NZVC | idsx |
| SUB r | 00100 | NZVC | idsx |
| AND r | 00101 | NZ | idsx |
| OR r | 00110 | NZ | idsx |
| NOT r | 00111 | NZ | - |
| ASL r | 01000 | NZVC | - |
| ASR r | 01001 | NZC | - |
| LDBYT r | 01010 | NZ | idsx |
| STBYT r | 01011 | - | dsx |
| LOADB | 01100 | NZ | idsx |
| ADDSP | 01101 | NZVC | i |
| BR | 01110 | - | ix |
| BRLE | 01111 | - | ix |
| BRLT | 10000 | - | ix |
| BREQ | 10001 | - | ix |
| BRNE | 10010 | - | ix |
| BRGE | 10011 | - | ix |
| BRGT | 10100 | - | ix |
| BRV | 10101 | - | ix |
| BRC | 10110 | - | ix |
| COMP r | 10111 | NZVC | idsx |
| JSR | 11000 | - | ix |
| RTS | 11001 | - | - |
| RTI | 11010 | - | - |
| CHARI | 11011 | - | dsx |
| CHARO | 11100 | - | idsx |
| DECI | 11101 | NZV | dsx |
| DECO | 11110 | - | idsx |
| HEXO | 11111 | - | idsx |
Instruction Set Details[edit]
Four addressing modes are available. These are:
- i, immediate mode, where the operand is stored directly following the opcode in memory.
- d, direct mode, where the immediate operand is a pointer to data in memory.
- s, stack relative mode, where the immediate operand is added to the SP register to generate a memory address.
- x, indexed mode, where the B register is added to the X register to obtain a memory address.
These memory modes are specified by bits 0 and 1 of the opcode: 00=i, 01=d, 10=s, and 11=x.
External links[edit]
Notes[edit]
- ↑ Dale, Nell, and John Lewis. Computer Science Illuminated. 3rd ed. Sudbury, MA: Jones and Bartlett, 2007. Print.
- ↑ Westwood Public Schools[permanent dead link]
- ↑ Warford, J. Stanley. Computer Systems, 1st ed. Jones & Bartlett. Search this book on
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