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Dual pipelining

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Dual pipelining or dual pipeline is one of computer pipelining technique to execute instructions in parallel.[1][2][3] In case of instruction level parallelism, this world is almost equivalent to superscalar.[4]

In 1993, Intel P5 microarchitecture Pentium processors is introduced with dual-pipeling.[4] This technology allows the processor to break down a command into two shorter commands and execute them simultaneously when it receives a long command. If there are separate tasks that must be completed for a result that are independent of one another, they can be executed simultaneously to save time.

Here is an example. Suppose a command is given to find the result of 14 * 27 + 512^2. The order of operations requires that 512^2 must be done first and then 14 and 27 must be multiplied. The result of those two actions would then be added together. This takes three steps. With dual pipelining, the first two actions would be computed simultaneously by different pipelines and then those would be added together. This case takes only two steps, saving one step. In a more complex command, many more steps can be saved.

See also[edit]

  • Parallelism (computing)
    • Instruction-level parallelism
      • Instruction pipeline
        • Pipelining
          • Classic RISC pipeline
          • Superscalar
    • Graphics pipeline
      • Geometry pipelines
    • Pipeline (software)
      • Pipeline (Unix)
      • Hartmann pipeline for VM
      • BatchPipes for MVS

References and notes[edit]

  1. Widergren, Robert D.; Chen, Wen-Hsiung; Fralick, Stanley C.; Tescher, Andrew G. (1978-12-15). "Discrete cosine transformer" (PDF). patents.google.com. United states patent and trademark office. pp. 5, 7. Claim 2:
    The circuit set forth in claim 1 wherein each said shuffle and add circuit means comprises an input data bus and an output data bus, dual storage memory means each connected to said input data bus, dual pipeline register means each connected to a said memory means, and an arithmetic logic unit circuit means connected to said pipeline register means for adding and subtracting said data in accordance with said method and putting resultant data out on said output data bus.
  2. Jiang, Weirong; Prasanna, Viktor K. (24 February 2009). "Large-scale wire-speed packet classification on FPGAs" (PDF). Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09. https://dl.acm.org/citation.cfm?id=1508162: ACM. pp. 219–228. doi:10.1145/1508128.1508162. ISBN 9781605584102.
    This paper exploits the features provided by current FPGAs and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification.
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  3. Nojiri, Naoto; Meng, Lin; Yamazaki, Katsuhiro (22 February 2015). "FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only)". Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '15. ACM. p. 267. doi:10.1145/2684746.2689118. ISBN 9781450333153.
    This research aims to detect BLOBs as fast as possible by using dual-pipelining image processing on the FPGA.
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  4. 4.0 4.1 Docter, Quentin; Dulaney, Emmett; Skandier, Toby (2008). CompTIA A+ Complete Study Guide: Exams 220-601 / 602 / 603 / 604. John Wiley & Sons. ISBN 9780470297537.
    With the release of the Pentium chips, dual pipelining was introduced (also called superscalar architecture), allowing the chip to process two operations at once.
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